Infineon Technologies Ag

Reinhard Kussian

Juergen Schaefer

Ketan Dewan

Dietmar Straeussnigg

Andrea Manzini

A digital filtering device includes at least one processor, a sample buffer configured to store samples, the sample buffer being a circular buffer, and a coefficient array for storing coefficients of a digital filter. The coefficient array includes a set of digital filter coefficients and a copy of the set of coefficients. For each of a plurality of input samples, the at least one processor can obtain a sample and store the sample as a value in a sample buffer at a position indicated by a buffer pointer, calculate an output sample comprising to perform a multiply-accumulate (MAC) operation with values currently stored in the sample buffer and a subset of the coefficients stored in a coefficient array, wherein a position of the subset of coefficients in the coefficient array is indicated by a coefficient pointer; and update the buffer pointer and the coefficient pointer.

Devices, systems, and methods for digital filtering

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter having an input coupled to an output of the first digital filter. A common gain is applied to signal samples passing between the first digital filter and the second digital filter, the common gain corresponding to a product of an output gain associated with the first digital filter and an input gain associated with the second digital filter. In another example, a digital filter includes an adjustable input gain element and an adjustable output gain element. The adjustable input gain element is configured to apply a gain value to an input signal sample, the gain value comprising a resultant difference of a bitshift configured for the digital filter and a bitwidth extension value. The adjustable output gain element is configured to apply an opposite of the gain value to an output signal sample.

Filter chains with improved signal to noise ratio

In various embodiments, a circuitry configured to generate a voltage is provided. The circuitry may include a sequence generator configured to provide a sequence of data words consisting of bits. The number of bits is greater than two. The circuitry may further include a delta-sigma modulator configured to receive the sequence of data words provided by the sequence generator and to provide a delta-sigma modulated first single bit data stream at a first data rate, and a decimation filter configured to generate a stream of decimated data words from the first single bit data stream at a second data rate. The second data rate may be smaller than the first data rate, each decimated data word including a plurality of bits. The circuitry may further include a parallel-to-serial converter configured to convert the decimated data words to a second single bit data stream while preserving the second data rate.

Circuitry, sensor system, method of generating a voltage, and method of operating a sensor system

A filtering method and a filter are disclosed. The method includes integrating values of an input signal by an integrator comprising a memory; storing an integration value in the memory; cyclically resetting the memory after integrating a first predefined number of values of the input signal; in a steady operating mode, generating a value of an output signal based on the integration value stored in the memory each time after integrating the first predefined number of values of the input signal; and in an initial operating mode, generating an initial value of the output signal based on the integration value stored in the memory after integrating a second predefined number of values of the input signal, wherein the second predefined number is smaller than the first predefined number.

Filtering method and filter

A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

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Klagenfurt, Austria

Reinhard Kussian