Infineon Technologies Ag

Reinhard Düregger

Alexander Benedix

Wolfgang Ruf

Stefan Dankowski

Robert Hermann

Henning Hartmann

Disclosed is a test method for testing a data store having an integrated test data compression circuit where the data store has a memory cell array with a multiplicity of addressable memory cells, read/write amplifiers for reading and writing data to the memory cell via an internal data bus in the data store and a test data compression circuit which compresses test data sequences, which are each read serially from the memory cell array, with stored reference test data sequences in order to produce a respective indicator data item which indicates whether at least one data error has occurred in the test data sequence which has been read.

Testing a data store using an external test unit for generating test sequence and receiving compressed test results

A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.

Memory system for network broadcasting applications and method for operating the same

A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.

Method for testing a device and a test configuration including a device with a test memory

To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines&#x2014;used in the process&#x2014;of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.

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Poing, Germany

Reinhard Düregger