Infineon Technologies Ag

Reinhard Dueregger

Alexander Benedix

Wolfgang Ruf

Stefan Dankowski

Roland Barth

Kapil Gupta

Markus Sickmoeller

Stephan Grosse

A method for replacing defective memory cells of a random access memory device of a data processing apparatus, in which, during the operation of the data processing apparatus, a defective memory cell is replaced by a replacement memory cell in the random access memory device by using a control instruction.

Method for replacing defective memory cells in data processing apparatus

A method for classifying semiconductor components by their performance characteristics includes reading an identifier associated with a component and storing, in conjunction with the identifier, first and second performances values for that component. These performance values represent the component's achieved operating speed at each of two different temperatures. The component is then allocated to a speed category on the basis of the first and second performance values.

Method for classifying components

A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step for providing redundant memory cells in the memory device. The method can also include a step for localizing defective cells. Further, the method can include a step of accessing the redundant memory cells by means of a predeterminable access mode. The method can also include a step of bypassing defective memory cells of the memory device in a manner dependent on the predeterminable access mode during operation of the memory device for accessing redundant memory cells and for replacement by redundant memory cells. Further, the method can include a step for providing redundant memory cells for storing additional information describing a defect correction.

Method for storing data in a memory device with the possibility of access to redundant memory cells

The present invention relates to an interconnect structure for an integrated circuit ( ) having a first interconnect (B ; B &prime;; B &Prime;), which is composed of a plurality of interconnect sections (A -A ; A &prime;-A &prime;; A &Prime;-A &Prime;) lying in a first and a second interconnect plane (M , M ); and a second interconnect (B ; B &prime;; B &Prime;), which runs adjacent to the first interconnect (B ; B &prime;; B &Prime;) and which is composed of a plurality of interconnect sections (A -A ; A &prime;-A &prime;; A &Prime;-A &Prime;) lying in the first and second interconnect planes (M , M ); the first and second interconnects (B ; B &prime;; B &Prime;; B ; B &prime;; B &Prime;) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A , A , A ; A &prime;, A &prime;, A &prime;; A &Prime;, A &Prime;) of the first interconnect (B ; B &prime;; B &Prime;) which lie in the first interconnect plane (M ) run at least in sections beside the interconnect sections (A , A ; A &prime;; A &prime;; A &Prime;, A &Prime;) of the second interconnect (B ; B &prime;; B &Prime;) which lie in the second interconnection plane (M ), and that the interconnect sections (A , A , A ; A &prime;, A &prime;, A &prime;; A &Prime;, A &Prime;) of the first interconnect (B ; B &prime;; B &Prime;) which lie in the second interconnect plane (M ) run at least in sections beside the interconnect sections (A , A , A ; A &prime;, A &prime;, A &prime;; A &Prime;) of the second interconnect (B ; B &prime;; B &Prime;) which lie in the first interconnect plane (M ). The invention also provides a corresponding fabrication method.

Interconnect structure for an integrated circuit and corresponding fabrication method

A method for integrating imperfect semiconductor memory devices having functional and defective memory cells into a data processing apparatus. The defective memory cells are assigned defect addresses or defect address ranges. Before a memory access of the data processing apparatus is carried out, the address of the memory access is compared with the defect addresses or defect address ranges and is recoded in the event of correspondence.

Method for integrating imperfect semiconductor memory devices in data processing apparatus

According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.

Dynamic memory device and method for controlling such a device

A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.

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Poing, Germany

Reinhard Dueregger