Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Reinhard C Schumann

Frank C Bomba

Andrew Halstead Mason

Paul Binder

James Jonathan Delmonico

Richard J Dischler

Dileep P Bhandarkar

Stephen R Jenkins

Stanley A Lackey

Steven R Jenkins

Diethelm G Ringleb

John Sweeney

Elsworth Stearns

Yong S Oh

Jeffrey W Mitchell

J J Grady, Iii

Michael E Hazen

Arnold J Smith

Dean A Sovie

Jim Klumpp

Tom Stylianos, Jr

Mark J Kelley

A computer system including a microprocessor and a circuit to provide a clock signal for the microprocessor is described. The circuit is responsive to a control signal for selecting a minimum clock signal frequency value and a maximum clock signal frequency value, with the maximum clock signal frequency value being adjusted in accordance with operating conditions of the central processor. Also the system includes a circuit which varies a magnitude of a supply voltage fed to the microprocessor in accordance with the temperature of the microprocessor and the operating frequency of the microprocessor. This arrangement provides an advantage to save power in computers. It is particularly advantageous for portable computers such as notebook computers to conserve battery charge, minimize heat dissipation in the microprocessor, and to minimize the size and weight of the battery used in the notebook for a given operating duration requirement.

Variable frequency clock control for microprocessor-based computer systems

A cache memory controller in which data processing systems having active power management may efficiently flush a cache during a shut down operation. A cache map divides the cache into a number of blocks and an inclusion bit is stored for each block. The block inclusion bit is set whenever a cache line in the block is fetched. As a result, when it is time to flush the cache during a time critical power management operation, the software need only flush those sections of the cache where the block inclusion bit has been set.

Inclusion map for accelerated cache flush

A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state. The system software determines the desired period of time to put the central processing unit into the low-power consuming safe and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention. When one of these conditions arises, the signal line changes polarity, the power supply and/or clock circuitry returns normal operating levels to the CPU, and the system bus interface presents all interrupts that asserted while the CPU was in the low-power consuming state to the CPU so it can continue normal operation.

Skipping clock interrupts during system inactivity to reduce power

A memory controller for optimizing direct memory access (DMA) read transactions wherein a number of cache lines are prefetched from a main memory as specified in a prefetch length field stored in a page table. When all prefetch data has been fetched, the memory controller waits to determine whether the initiator of the DMA read transaction will request additional data. If additional data is needed, additional cache lines are fetched. Once the initiator terminates the DMA read transaction, the prefetch length field for a selected page other entry in the table is updated to reflect the actual DMA read transaction length. As a result, an optimum number of cache lines are always prefetched thereby reducing the number of wait states required.

Prefetch management for DMA read transactions depending upon past

A technique for implementing a programmable thermal model of an integrated circuit component such as a central processing unit (CPU) and its associated heat sink. The model estimates the die temperature of the component as if there were no cooling devices present in the system such as a forced air cooling fan by integrating the thermal energy added when the component is active and by integrating the thermal energy removed when it is idle. A programmable power value may be used to represent the heat added to the model at each model sample period. The effect of a heat sink in cooling the idle component may be modeled by reducing the value of the heat accumulator by a predetermined fractional amount during each sample period. The decay time constant for the model may be changed by then adjusting the sample period. With an accurate model estimate predicting the component temperature in the absence of cooling being instantaneously available, any associated cooling device such as a fan can be operated in such a manner as to turn on only when it is estimated to actually be needed and to be kept off at all other times. In addition, a turn off delay can be implemented in order to avoid undesirable cycling effects.

Thermal model for central processing unit

A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state. The system software determines the desired period of time to put the central processing unit into the low-power consuming state and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention. When one of these conditions arises, the signal line changes polarity, the power supply and/or clock circuitry returns normal operating levels to the CPU, and the system bus interface presents all interrupts that asserted while the CPU was in the low-power consuming state to the CPU so it can continue normal operation.

A memory controller such as for use with a synchronous dynamic random access memory (SDRAM) wherein an active row at the end of each transfer can either be left active or closed by precharging the row. The memory controller uses a history register to keep track of the results of a number of prior accesses to each memory bank, remembering whether the access was to the same row as an immediately prior access. For each new memory access, the memory controller either asserts or deasserts a precharge enable signal depending on the state of the history bits. As a result, the memory controller is more likely to have a correct row open on a subsequent access, and less likely to have a wrong row open.

Adaptive precharge management for synchronous DRAM

A method of performing continuity testing of individual lead sets bonded to an integrated semiconductor component with a continuity test circuit fabricated on the component. The continuity test circuit includes a plurality of current gates, each of which is associated with a different semiconductor component contact pad a lead set is bonded to. Each current gate includes a first terminal connected to the associated contact pad and a second terminal connected to a common conductor all the current gate second terminals are connected to. The common conductor terminates at a semiconductor component contact test pad a lead set is bonded to. Whenever a test signal is applied to either the first or second terminal of a current gate, a measurable response signal is generated by the current gate over the other terminal. Continuity testing of the lead sets bonded to the chip is performed by applying a test signal to either a wiring board conductor connected to the lead set being tested or a wiring board conductor connected to the lead set connected to the semicondcutor component test contact pad. A test probe is then applied to the board conductor the test signal is not applied to. If the response signal is sensed, the leads are properly bonded; if no response signal is detected either the lead set being tested on the lead set connected to the semiconductor component is improperly bonded. The current gate blocks signals on the first terminal from appearing on the second terminal or the common conductor. Thus, when the semiconductor component is in use, the continuity test circuit is isolated from the other individual circuit components forming the integrated semiconductor component.

Method and on-chip apparatus for continuity testing

A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Bus device for use in a computer system having a synchronous bus

Control of a communications path interconnecting separate devices in a digital computer system is provided by only two signals generated and received locally within each device on the path and asserted on a systems-wide basis on two separate lines of the path. The generation and utilization of the control signals is independent of the physical location of the devices on the path, and position-dependent delays in transmission of the signals from one device to another are avoided.

Bus-control mechanism

One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.

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Stow, MA, United States of America

Reinhard C Schumann