Viavi Solutions Inc.

Viavi Solutions Deutschland Gmbh

Jdsu Deutschland Gmbh

Viavi Solutions Deustschland Gmbh

Reiner Schnizler

Paul Brooks

Bernhard Mayer

The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.

Slip detection on multi-lane serial datalinks

An apparatus such as an Optical Network Tester (ONT) may include an embedded script interpreter to interpret a script for testing an optical transponder coupled to the ONT. The ONT may identify a control based on a statement included in the script, and cause, via an electrical interface, an interaction with the optical transponder to occur based on the control. The ONT may generate a first timestamped log entry to indicate a timing of the control, detect a data path event associated with the optical transponder, generate a second timestamped log entry to indicate a timing of the data path event, and determine that the data path event was caused by the control based on the first timestamped log entry and the second timestamped log entry. The ONT may further assess operation of the optical transponder based on the determination that the data path event was caused by the control.

Transponder management testing and interaction tracing

The disclosure relates to evaluating bit error vectors for symbol error analysis on real-world framed signals. Forward error correction (FEC) may generate a bit error vector to correct binary lanes such as non-return-to-zero (NRZ) lanes demultiplexed from a symbol-encoding lane such as a 4-level pulse amplitude modulation (PAM-4) lane. An apparatus may apply the bit error vector to the demultiplexed NRZ lanes to identify bit errors that occurred on the NRZ lanes. The apparatus may map the bit errors on the NRZ lanes to symbol errors on the PAM-4 lane. The apparatus may generate detailed symbol error information based on the identified symbol errors. The symbol error information may then be used for link tuning, thereby mitigating the effects of high frequency physical effects and other impairments on high-speed data links.

Evaluation of bit error vectors for symbol error analysis

The disclosure relates to detecting phase slips in a data link. An apparatus may perform a frame resynchronization when a phase slip is detected. The apparatus may generate a reference phase signal that is compared to incoming data frames to determine whether a phase slip occurred and characterize the phase slip. The counter may be based on a recovered receiver clock, thereby counting an actual number of bits received, and may wrap based on the frame size. A value of the counter latched to an incoming frame before the frame resynchronization may be compared to a latched value of the counter after the frame resynchronization to determine whether a phase slip, a size of the phase slip, and a direction of the phase slip.

Slip detection on high speed data links

A test instrument measures performance of a transponder without direct access to a line interface of the transponder. The test instrument learns parameters of internal signal conversion processes of the transponder and measures performance of the transponder based on the learned parameters.

Test instrument for testing devices internally performing signal conversions

A test instrument performs a power supply stress test by invoking current surges in a device under test. The current surges are invoked by stimulating functional blocks in the device under test with test signals received via a network interface of the device under test.

Power supply stress testing

A test device for testing a device under test (DUT) includes an integrated control interface adaptable for a plurality of different communication standards. The integrated control interface can be adapted to be compliant with the communication standard used by a DUT connected to the test device.

Test device and method

The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.

Bit error pattern analyzer and method

A test device is provided for testing a device under test (DUT) having a control interface compliant with a standard selected from a plurality of standards each supporting a common set of management data input/output (MDIO) and non-MDIO control signals. The test device includes a test interface and an integrated control interface. The integrated control interface adapts to the standard with which the control interface of the DUT complies, so that the integrated control interface directly and fully controls the DUT via at least the common set of MDIO and non-MDIO control signals. The integrated control interface exchanges control signals selected from the common set of MDIO and non-MDIO control signals with the control interface of the DUT to monitor the DUT and thereby obtain status information about the DUT.

For an apparatus which communicates data of a number of virtual lanes over a number of physical lanes, where the number of virtual lanes is different than the number of physical lanes and where a mapping between the virtual lanes and the physical lanes is not fixed, a method is provided for ascertaining the mapping between the virtual lanes and the physical lanes. The method includes: applying an impairment to a communication capability of one of the physical lanes so as to increase bit errors for data communicated via said one physical lane; determining a test bit error rate for each of the plurality of virtual lanes while the impairment is applied to the communication capability of the one physical lane; and ascertaining from the test bit error rates which of the virtual lanes is/are mapped to the one physical lane whose communication capability was impaired.

Growing community of inventors

Beuren, Germany

Reiner Schnizler