Micronas Gmbh

Denso Corporation

Tdk-micronas Gmbh

Reiner Bidenbach

Klaus Heberle

Martin Bayer

Joerg Franke

Ulrich Theus

Joachim Ritter

Hans-Jörg Fink

Stefan Kredler

Jens Schubert

Yoshiyuki Kono

Manfred F Ullrich

Thilo Rubehn

Ralf Janke

Jörg Franke

Laurent Avon

Christian Jung

Hans-Jörg Dipl-Ing Fink

Martin Dipl-Ing Bayer

A monolithic sensor arrangement includes a housing, a sensor integrated in the housing, and two or three connecting contacts deployed on the housing so as to provide a contact with the sensor. The housing also includes an integrated digital circuit includes a freely programmable digital processor, a program memory and a data memory, which are used to control and/or process the functionalities and/or the measured data of the sensor.

Monolithic sensor arrangement and method for controlling a monolithic sensor arrangement

A semiconductor component on a semiconductor chip comprises at least one sensor element for measuring a physical quantity and an evaluator. The semiconductor component can be switched between a first and a second operating mode. In the first operating mode, the sensor element is sensitive to the physical quantity to be measured and a measurement signal output of the sensor element is connected to an input connection of the evaluator. In the second operating mode, the sensor element is not sensitive to the physical quantity to be measured and/or the signal path between the measurement signal output and the input connection is interrupted. A test signal source for generating a test signal simulating the measurement signal of the sensor element is arranged on the semiconductor chip. In the second operating mode, the test signal source is connected or capable of being connected to the input connection of the evaluator.

Self-testing sensor apparatus and method

Disclosed is a method and device for transmitting data between at least two transmitters and a receiver which are connected to a bus. A synchronization signal is applied to the bus and a number of data volume counters corresponding to the number of transmitters reduced by one is set to a predefined initial value. A first transmitter transmits in the form of data elements a predefined data volume allocated to the transmitter over the bus to the receiver. The data volume values of the other transmitters are selected so that only one transmitter at any given time simultaneously transmits on the bus.

Communication device and method for improved synchronous data transmission

Disclosed is an integrated electronic circuit comprising a core circuit that generates a useful signal as well as a buffer for storing the useful signal. The buffer stores the last read value of the useful signal for a predetermined period of time when the power supply is interrupted, and the buffer is disconnected from the power supply of the other circuits.

Integrated electronic circuit

A semiconductor component has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination surface is connected in an electrically conductive manner to an analysis contact that projects above the surface of the semiconductor chip, that is located in the interior of the encapsulating compound at a distance from its exterior surface, and that can be exposed by removing a layer of the encapsulating compound located near the exterior.

Semiconductor component

A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells () in a nonvolatile memory device (). Parallel to the programming (P) or deletion (L) operations of the actual memory cells () the respective programming or deletion process is carried out on at least one similar checking cell (), with the programming (P) or deletion (L) operations being less favorable by a defined extent than the programming (P) or deletion (L) operations of the actual memory cells (). From the content of the checking cell () an evaluation device () determines whether the programming (P) or deletion (L) operation was successful or not, and a corresponding output signal (ak) indicative thereof is produced.

Nonvolatile memory device comprising a programming and deletion checking option

A digital-to-analog converter circuit layout includes a ratiometric digital-to-analog converter. The ratiometric digital-to-analog converter includes a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module. The a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module is configured in a controllable manner for converting digital data received at the input to a converter output voltage at the output using a reference voltage, an adjustable current as a reference current, and an adjustable impedance value. The circuit layout is characterized in that the voltage controlled oscillator includes circuit components which multiply the reference voltage by a quotient between the adjustable impedance value and the adjustable current, and which apply the multiplication results to the pulse width modulation module.

Digital-to-analog converter circuit layout

The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C, C) for data and/or signal exchange with external components and setups. At one of the terminals (C), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V, V) that can be controlled and which are different from a supply voltage level (V) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.

Circuit configuration with serial test interface or serial test operating-mode procedure

A method for testing a Hall magnetic field sensor on a wafer includes generating a current flow in a Hall plate of the Hall magnetic field sensor. At least one voltage value across first and second nodes is measured and a measured voltage signal is provided indicative thereof. An electrical resistance based upon the measured voltage and the current is then determined, in the absence of an applied test magnet field.

Method and apparatus for testing a hall magnetic field sensor on a wafer

A phase-locked loop with a delay element (DLL) is described which is essentially characterized in that the delay element () has a chain of a number n delay units (), the outputs () of which are fed to a locking monitoring circuit () which determines whether the delay time Tof the delay element () lies within a range a*T&#x3c;T&#x3c;b*T, where 0.5&#x3c;a&#x3c;1 and 1&#x3c;b&#x3c;2, and wherein the locking monitoring circuit () performs a correction of this delay time when this condition is not met.

Phase regulating circuit with a time-delay element

In integrators which integrate the analog photocurrent of a photodiode (PD), the amplification-bandwidth product is relatively small on account of the parallel parasitic capacitance (Cp) of the photodiode (PD). However, in a design with a switched capacitor (C ), the bandwidth and at the same time the DC amplification must be large, so as to assure the integrator function even at low frequencies. So as to fulfill both of these mutually contradictory requirements for large bandwidth and high DC amplification, a reference voltage (V ) is present at a voltage divider that includes a resistor (R ) and a circuit section (R ) connected in series thereto, as well as at the photodiode (PD). The connection point of the voltage divider is connected to the inverting input of the transconductance amplifier (V). In a preferred embodiment, the circuit section (R ) is realized as a switched capacitor (C ), and the resistance (R ) is realized as an MOS transistor (T ). As an integrated switching circuit, the invention is especially suited for sigma-delta-analog converters.

Analog integrator circuit

A function generator includes a switching stage for forming a defined signal waveform. The switching stage includes switching transistors that are turned on in a predetermined sequence of undelayed and delayed clock signals, with an output node summing the output currents of the switching transistors. The function generator also includes a delay device that generates the undelayed and delayed clock signals from an applied clock signal. The delays of the delayed clock signals define predetermined instants within at least one period of the applied clock signal. The switching edge is divided into different time ranges whose respective edge steepnesses are adjustable independently of each other. By point-mirroring the signal waveform about a medium value of the signal edge, frequencies at twice, four times, six times, etc. the frequency of the fundamental signal frequency are reduced. Due to the sinusoidal shape of the switching edges, electromagnetic emissions are reduced because of the reduced amplitude of the harmonics. The electromagnetic emission reduction applies both to pure clock signals and to other digital signals, including control, data, or supply lines.

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Vörstetten, Germany

Reiner Bidenbach