Itt Industries, Inc.

Reiner Backes

Friedrich Schmidtpott

Herbert Elmis

Ulrich Langenkamp

Mathew Neal

A circuit is described which holds the bootstrap node of a MOS push-pull end stage at a constant potential even if the end stage has to generate an output H-level. A diode/capacitor charge pump circuit supplies the required pulse current only fed to the node in case of the output H-level.

MOS bootstrap push-pull stage

A delay circuit provides adjustable delay in constant increments. In order to achieve adjustable but constant delay times of a chain of inverter pairs, each pair is completed by a capacitor, a third inverter, and a transfer transistor the gate of which is fed by a voltage controlling the pair delay time. This voltage is generated by a control circuit measuring the actual delay time of the chain with respect to the period of a constant clock signal.

Integrated delay circuit for digital signals

A digital synchronization operation circuit synchronizes a pulse train with horizontal synchronizing pulses contained in a received standard television signal which, after being demodulated in the television receiver, is present as the composite color signal and which is fed to an analog-to-digital converter clocked by a clock signal. The digital synchronization separation circuit has an improved phase resolution such that the phase resolution is greater than the resolution provided by the pulse width of clocking signals.

Digital circuit for synchronizing a pulse train

Such digital filters process digital input data occurring during short pulses of a filter sampling signal (fa) in the pure binary code and in two's complement notation. They contain a parallel-to-serial converter (pw) at the input end, at least one adder (ad), at least one shift register used as a status register (z), at least one multiplier circuit (m1) to which an input-data-dependent signal and a factor which is constant at least during the multiplication are applied as a multiplier and a multiplicand, respectively, and a serial-to-parallel converter (sw) at the output end. The status register (z) has, in addition to a number of stages determined by the number of digits of the input data, a number of stages equal to the number of digits of the multiplicand. The parallel-to-serial converter (pw) is followed by a digit complementer (se) which increases the number of digits of the output signal of the parallel-to-serial converter (pw) to that of the status register (z). The function of the multiplier circuit is implemented with a sign-signal repeater (vw) and a tap on at least one stage (r) of the status register (z) which tap is connected to the input of the sign-signal repeater (vw). Associated with the outputs of the digit complementer (se), the status register (z), and the sign-signal repeater (vw) are the inputs of the adder (ad) and the subtracter (s), or vice versa. Particularly advantageous circuit structures for the stages of the above-mentioned subcircuits are provided for implementation in ratio-type dynamic insulated-gate field-effect transistor technology using a two-phase clock system.

Circuit arrangement for serial digital filters

This circuit, controlled by the counter (Z) and via the row transistors (ZTm) and upon actuation of a pushbutton key, successively interrogates the row lines (1m) and, via the column line (2n) as connected to the row line, forms an inverter with the corresponding resistor (SRn), so that an L level will appear at the input of the corresponding column inverter (SI1n). In the ROM-type matrix (M), with the aid of the matrix transistors (T . . . ) and the resistors (MRmn) it is accomplished that the m.multidot.n lines (Lmn) are only controlled in such a way that the corresponding line conducts an H level upon actuating only one single pushbutton key of the keyboard (TF). Accordingly, a l-ex-m-times-n code appears on the lines (Lmn) which, via the NOR gate (N) also effects the release of the counter (Z) counting the clock pulses of the clock pulse generator (TG).

Integrated circuit for a keyboard of an electronic apparatus

The circuit provides a signal (a) at the application of an interrogation pulse (as) if a change of state has occurred in a one-out-of-n system until the instant of interrogation. Each signal (1 . . . n) of the system is assigned an arrangement having storage capability and comprising two inverters (i1, i2) with feedback and two series-connected transistors (t2, t3) which are both conducting at the instant of interrogation and, thus, produce an unambiguous signal level at a common load resistor (l) only if a change of state has occurred in the system.

MOS Transition detector for plural signal lines using non-overlapping

A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1). The count-down output (RA) is coupled through a third transfer transistor (T2), controlled by the second clock signal (F2), to the first input of the second AND element (U2), whose second input is connected to the output of the NOR gate (NG) through a fourth transfer transistor (T 5), which is also controlled by the second clock signal (F2). One of the two inputs of the NOR gate is connected to the carry input (UE) in each stage. The carry input (UE) is connected to the carry output (UA) of the stage through a carry transfer transistor (UT). The carry input (UE) of the least significant stage is grounded. The second input of the NOR gate (NG) is connected to a stop line (S). The carry output (UA) is connected to a constant voltage (U) through a transfer transistor (T4) controlled by the countdown output (RA). In a second variant, the complex gate (KG) is omitted, so that the output of the first inverter (I1') is connected directly to the input of the second inverter (I2') through the first transfer transistor (T1'). The output of the NOR gate (NG') controls the gate of the second transfer transistor (T2'). Its first input is fed with the first clock signal (F1'), and its second input is connected to the carry input (UE). Those ends of the current paths of the second and third transfer transistors (T2', T3') not connected to the outputs are coupled to the input of the inverter (I1').

Dynamic synchronous binary counter with stages of identical design

The monolithic integrated binary MOS parallel comparator uses enhancement-mode insulated-gate field effect transistors of the same conductivity type and comprises n successively weighted stages each including a NOR block having at least two inputs each receiving a correspondingly weighted digit of a different one of a first and a second n-digit binary word and an additional logic circuit also receiving the correspondingly weighted digit of the first and second words, and an output logic circuit coupled to each of the n stages to provide an output signal for the comparator.

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Freiburg, Germany

Reiner Backes