International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Reinaldo Ariel Vega

Emre Alptekin

Takashi Ando

Robert Russell Robison

Rajasekhar Venigalla

Hari V Mallela

Praneet Adusumilli

Ravikumar Ramachandran

Viraj Yashawant Sardesai

Kangguo Cheng

Cung D Tran

Ruilong Xie

Henry K Utomo

Cheng Chi

Sameer Hemchand Jain

Michael A Guillorn

Ali Khakifirooz

Terence B Hook

Jianshi Tang

Veeraraghavan S Basker

Ruqiang Bao

Lawrence Alfred Clevenger

Nicholas Anthony Lanzillo

Albert Manhee Chu

Brent A Anderson

Li-Wen Hung

Jingyun Zhang

Michael Vincent Aquilino

Tenko Yamashita

Ramachandra Divakaruni

Dechao Guo

Herbert Lei Ho

David S Wolpert

Gen Tsutsui

Kern Rim

Andrew Mark Greene

John Edward Barth, Jr

Gauri V Karve

Gregory Costrini

Huiling Shang

Alexander Reznicek

Junli Wang

Choonghyun Lee

Richard Stephan Wise

Zhengwen O Li

Unoh Kwon

Huiming Bu

Byeong Yeol Kim

Lan Yu

Huimei Zhou

Miaomiao Wang

Wing L Lai

Bruce Bennett Doris

Nicolas J Loubet

Yun Yu Wang

Vijay Narayanan

Shom Ponoth

Evan G Colgan

Heng Wu

Bucknell Chapman Webb

Kisik Choi

Babar Ali Khan

Fuad Elias Doany

Koji Watanabe

Hiroyuki Miyazoe

Kafai Lai

Johnathan E Faltermeier

Xinhui Wang

Daniel J Jaeger

Xiaobin Yuan

Kehan Tian

Derrick Liu

Jian Yu

Hung H Tran

Adra Carr

William L Nicoll

Dong-Ick Lee

Pooja R Batra

Edward J Nowak

Juntao Li

Chanro Park

Julien Frougier

Keith Kwong Hon Wong

Dominic Joseph Schepis

Kevin W Brew

Abhishek Dube

Zhijian Yang

Hongwen Yan

Yong Meng Lee

Keith Howard Tabakman

Xiang Hu

Pietro Montanini

Ying Li

Leon Jacob Sigal

Yunsheng Song

Eric C Harley

Yue Ke

Matthew W Stoker

Melissa Alyson Smith

Yao Yao

A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

Dielectric tuning of negative capacitance in dual channel field effect transistors

One or more systems, devices, and/or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. According to one embodiment, a semiconductor device can comprise a field-effect transistor (FET), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (FET) relative to a gate of the FET to mitigates parasitic capacitance within the device.

Reduced capacitance between power via bar and gates

A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate, a backside wiring layer below a backside power delivery network, and a contact via extending between the gate contact and the backside wiring layer.

Backside self aligned skip via

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Source/drain contact at tight cell boundary

A structure is provided that includes a first metal level including a first metal line, a second metal level spaced apart from the first metal level and including a second metal line, and a first metal via structure connecting the first metal line to the second metal line. The first metal via structure directly contacts a sidewall surface and a horizontal surface of the first metal line.

Wrap around metal via structure

A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Vertical transport field effect transistor (VTFET) with backside wraparound contact

A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

Wraparound contact with reduced distance to channel

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

Pass-through wiring in notched interconnect

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Vertical-transport field-effect transistor with backside gate contact

An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Decoupling capacitor inside gate cut trench

A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

Negative capacitance for ferroelectric capacitive memory cell

A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Phase change memory cell with superlattice based thermal barrier

A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

Random weight initialization of non-volatile memory array

An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.

Buried local interconnect between complementary field-effect transistor cells

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Wappingers Falls, NY, United States of America

Reinaldo Ariel Vega