Toshiba Memory Corporation

Reina Nishino

Kenichi Maeda

Toshio Fujisawa

Nobuhiro Kondo

Kenji Funaoka

Hiroyuki Sakamoto

Hiroto Nakai

Atsushi Kunimatsu

Hiroshi Nozue

Tsutomu Owa

Masaki Miyagawa

Mari Takada

Tsutomu Unesaki

Kazuhiro Kawagome

Yuji Izumi

A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Memory management device predicting an erase count

According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.

Memory device, and information-processing device

According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.

Memory system

Growing community of inventors

Yokohama, Japan

Reina Nishino