Kabushiki Kaisha Toshiba

Reiko Nojima

Masaaki Yamada

Hideki Takeuchi

Mutsunori Igarashi

Masami Murakata

Takashi Ishioka

Sachio Hayashi

The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent so as to make the numbers of '0' and '1' in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same

A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same

In a semiconductor integrated circuit comprising: a logic circuit which performs prescribed logical operations; first power supply lines (fundamental power lines) which supply source power to the logic circuit; and second power supply lines which are provided, on the logic circuit, in a wiring level different from that for the first power supply lines and also which are interconnected with the first power supply lines through contact holes at the intersections therebetween, the number and the positions of the contact holes can be determined so as to minimize the voltage drop value at the logic circuit. As a result, the voltage drop can be relaxed, thus assuring stable operations of the circuit.

Integrated circuit, design method for the same, and memory storing the

A layout pattern generation method and device executing this method in which a symbolic layout of a semiconductor integrated circuit is generated, the sizes of transistors are changed by using the circuit connection information of the layout pattern, the correspondence information of the transistors whose sizes have been changed are generated by using the symbolic layout and the changed circuit connection information, the symbolic layout after the transistor sizes have been changed is generated by using the correspondence information, the generated symbolic layout is compacted, and then a new layout pattern is generated by using the compacted layout pattern.

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Tokyo, Japan

Reiko Nojima