Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Reika Ichihara

Masato Koyama

Yoshinori Tsuchiya

Akira Nishiyama

Takayuki Tsukamoto

Kikuko Sugimae

Shosuke Fujii

Yuuichi Kamimuta

Hiroshi Kanno

Kenichi Murooka

Koji Asakawa

Yoshihisa Iwata

Satoshi Mikoshiba

Hideyuki Nishizawa

Daisuke Matsushita

Hiroki Tanaka

Shigeki Hattori

Masaya Terai

Yoshiaki Fukuzumi

Hideaki Aochi

Katsuyuki Sekine

Hirofumi Inoue

Akira Takashima

Takayuki Miyazaki

Tsukasa Tada

Takashi Yamauchi

Hiroyuki Fuke

Takayuki Ishikawa

Kosuke Tatsumura

Hidenori Miyagawa

Masamichi Suzuki

Yuuichiro Mitani

Tetsuya Hayashi

Takeshi Yamaguchi

Shinichi Yasuda

Kazuaki Nakajima

Chika Tanaka

Masato Oda

Shinya Aoki

Koichiro Zaitsu

Mari Matsumoto

Yusuke Arayashiki

Kensuke Ota

Shigeru Kawanaka

Hirotaka Nishino

Haruka Kusai

Masakazu Goto

Shuichi Toriyama

Jiezhi Chen

Masahiko Yoshiki

Haruka Sakuma

Takashi Haimoto

Takashi Shigeoka

Dandan Zhao

According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.

Memory element

According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.

Read circuit for a variable resistance memory device

A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Semiconductor device

According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Resistance-change memory operating with read pulses of opposite polarity

A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.

Resistance random access memory device and method for operating same

According to one embodiment, a semiconductor memory device includes a plurality of first wirings, a plurality of second wirings, a variable resistance layer, a first barrier insulating layer, and a second barrier insulating layer. The first wirings are disposed at predetermined pitches in a first direction intersecting with a substrate. The second wirings are disposed at predetermined pitches in a second direction intersecting with the first direction. The second wirings are formed to extend in the first direction. The variable resistance layer is disposed between the first wiring and the second wiring. The variable resistance layer is disposed at a position where the first wiring intersects with the second wiring. The first barrier insulating layer is disposed between the first wiring and the variable resistance layer. The second barrier insulating layer is disposed between the second wiring and the variable resistance layer.

Semiconductor memory device and method of controlling the same

A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.

Semiconductor storage device and driving method of the same

A semiconductor memory device according to the embodiments includes a first wiring, a second wiring that extends to intersect with the first wiring, a memory cell that is disposed on each intersection portion of the first wiring and the second wiring, and includes a variable resistive element, and a control circuit to control a voltage applied to the memory cell. The control circuit applies a read voltage with respect to the memory cell for a plurality of times to determine a resistive state of the memory cell for a plurality of times, so as to obtain a first determination result or a second determination result. The control circuit compares the number of the first determination result with the number of the second determination result, terminates a reading operation when the comparison result satisfies a certain condition, and starts the reading operation again when the condition is not satisfied.

Resistance-change memory having on-state, off-state, and intermediate state

A resistance variable memory has a controller configured to control a voltage to be applied to the memory cell. The controller has a reset operation to bring the memory cell into a reset state, a first operation to apply a set voltage between the first wire and the second wire, a second operation to determine whether a current flowing to the memory cell to be set exceeds a first threshold when a first reading voltage is applied between the first wire and the second wire, a third operation to determine whether a current flowing to the memory cell to be set exceeds a second threshold when a second reading voltage is applied between the first wire and the second wire, and a fourth operation to apply a second reset voltage, between the first wire and the second wire.

Variable resistance memory device and verify method thereof

According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.

Nonvolatile semiconductor memory device and method for manufacturing same

A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line.

Reconfigurable circuit and method of programming the same

A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.

Non-volatile semiconductor memory device

According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Semiconductor storage device

Growing community of inventors

Yokohama, Japan

Reika Ichihara