Matsushita Electric Industrial Co., Ltd.

Reiji Segawa

Toshiki Mori

Tsutomu Fujita

Ichiro Nakao

Ichiro Okabayashi

Masahide Kakeda

Tatsuhiko Nagahisa

The present invention has for its object to provide a data processing apparatus which improves the point that in data processing employing an associative storage device, performing the high speed processing has been impossible in the full-associative constitution since each way (entry) is subjected to the sequential processing respectively in search processing. The data processing apparatus includes a TLB comprising an information pair specifying information means (RP), a first information holding means (PTE-Hi), and a second information holding means (PTE-Lo). The high speed processing against information held in a TLB memory section is realized by performing the search processing employing information held in the above-mentioned means.

Data processing device and method

An address translation apparatus comprises: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier which is composed of plural bits; comparison information storage means for storing comparison information which defines a method for comparing a process identifier possessed by a process that is currently executed, with the process identifier in each entry; process comparison means for comprising the process identifier possessed by the process that is currently executed, with the process identifier in the entry, on the basis of the comparison information; and entry retrieval means for retrieving, from the entry storage means, an entry including a virtual page number equal to a virtual page number supplied from the outside, and a process identifier which matches the process identifier of the currently executed process, according to the result of comparison by the process comparison means. Therefore, when a physical memory has a content which can be shared between at least two processes, effective utilization of memory area can be achieved by unifying entries with respect to these processes.

Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit

The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.

Semiconductor device and method for fabricating the same, memory core chip and memory peripheral circuit chip

A layout input apparatus of the present application includes: an input section for inputting first coordinate information representing a position of a first circuit portion included in a first semiconductor integrated circuit and second coordinate information representing a position of a second circuit portion included in a second semiconductor integrated circuit. The layout input apparatus further includes a control section for performing a predetermined coordinate transformation with respect to the second coordinate information; and a storage section for storing the first coordinate information as at least a part of first layout data representing a layout of the first semiconductor integrated circuit and storing the transformed second coordinate information as at least a part of second layout data representing a layout of the second semiconductor integrated circuit.

Layout input apparatus, layout input method, layout verification apparatus, and layout verification method

Semiconductor device and method for fabricating the same, memory core

A single data output terminal and an output portion having a pair of output control terminals for generating a ternary output, are disposed for a plurality of data input terminals and a plurality of control input terminals in the same number as that of the data input terminals. Input changeover portions have (i) a state where data signals can be entered into the output control terminals and (ii) a state where the data signals cannot be entered into the output control terminals. An input control portion supplies, according to the states of control signals entered therein, a changeover signal for switching the input changeover portions to (i) a mode in which one of the input changeover portions is set to the conductive state, or (ii) a mode in which all of the input changeover portions are set to the non-conductive state. According to the states of entered control signals, an output control portion controls the output portion such that a high impedance signal is supplied according to a changeover signal for setting all of the input changeover portions to the non-conductive state, and that there is generated an output signal identical with the value of an entered binary data signal according to a changeover signal for setting one of the input changeover portions to the conductive state.

Tri-state output buffer circuit

An output circuit for a data transfer device includes first and second control inputs, a data input and a data output. The first control input controls whether the data output is generated in accordance with an ordinary type or an open drain type circuit operation, while the second control input controls whether the data output generated in accordance with the ordinary type circuit operation is set to an active state or an inactive state.

Growing community of inventors

Nagaokakyo, Japan

Reiji Segawa