Infineon Technologies Ag

Reidar Stief

Peter Beer

Herbert Benzinger

Stephan Schroeder

Markus Rohleder

In a clock-synchronously operated semiconductor memory, particularly a DDR SDRAM, data are read in clock-synchronously with respect to a data strobe signal in the normal mode, according to standard. During the test mode, a DQ receiver is supplied with the operating clock signal instead of the DQS signal. A downstream memory element is bridged by a direct signal path. To change over, multiplexers/demultiplexers driven by the test mode control signal are provided. The data signal supplied to the memory cell array is available immediately after a write command has been applied to the memory cell array.

Circuit configuration for receiving a data signal

A circuit for synchronizing signals during an exchange of information between circuits, in particular between computer chips, of a system of circuits, is described. The configuration has a delay locked loop (DLL) circuit for synchronizing an internal clock between a respective circuit and an external clock of the circuit system according to the phase difference between the two clocks in a manner dependent on phase changes in the signals. A response sensitivity of the DLL circuit is defined by a filter, which enables a renewed synchronization only after the arrival of a plurality of phase change events. The filter provided for setting the response sensitivity of the DLL circuit is of a variable configuration.

Circuit for synchronizing signals during the exchange of information between circuits

An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to a sense amplifier via a controllable switching device. Furthermore, a control circuit is contained, having an output, which is connected to a control input of the respective switching device, and having an input, which is connected to a terminal for a test mode signal. The control circuit is configured in such a way that, within an access cycle, the respective switching device can be switched into a non-conducting state on account of an active state of the test mode signal. In the integrated memory, it is possible to measure the leakage behavior of a bit line during the read-out of a data signal.

Integrated memory and method for testing an integrated memory

A delay locked loop has a filter in order to set the delay time of a delay path in a manner dependent on the phase difference of input and output clock signals. The phase difference is ascertained by a phase detector. An additional control circuit determines the number of drive pulses of the filter and additionally controls the number of effective counter stages of a counter that forms the filter. The transient recovery time of the delay locked loop is thereby reduced.

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Munich, Germany

Reidar Stief