Intel Corporation

Reid J Reidlinger

Efraim Rotem

Krishnakanth Venkata Sistla

Alon Naveh

Vivek Garg

Rakesh Kumar

William Johnson Bowhill

Don Soltis

Satish Shrimali

Lokesh Sharma

Eric Fetzer

A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Managing power consumption in a multi-core processor

Growing community of inventors

Wellington, CO, United States of America

Reid J Reidlinger