Texas Instruments Corporation

Regis Gaillard

Nicolas Chauve

A digital system has a host processor with a bus controller and peripherals ( )- ( ) interconnected by an interconnect bus 32 peripherals are share a common strobe line (nSTROBE&lsqb; &rsqb;) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain can be likewise connected to interconnect bus Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller by CPU An interconnect bus transaction is synchronized in background so that a current cycle is not delayed. A first write cycle is completed as a no-wait state transaction, while immediately following second write cycle is delayed while synchronization circuit completes the synchronization of the first write cycle. nSTROBE pulse indicates first write transaction while nREADY pulse indicates the completion of a no-wait state first write transaction nSTROBE indicates the beginning of the second write transaction while nREADY pulse indicates the completion of a wait stated write, transaction Synchronization of write transaction is completed in background by using nSTROBE pulses and without the need for a free running clock signal from the host.

Transferring data between asynchronous devices

A digital system has a host processor with a bus controller and peripherals ( )- ( ) interconnected by an interconnect bus peripherals are share a common strobe line (nSTROBE &lsqb;0&rsqb;) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain , can be likewise connected to interconnect bus . Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller by CPU . A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state to transfer state along arc . The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt&equals;FIFO_size. Then the FIFO state machine controller transitions to end transfer state and asserts the END_DMA signal to stop the DMA transfer and then transitions to IDLE state

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La Gaude, France

Regis Gaillard