New Jersey Institute of Technology

Agere Systems Inc.

Other

Agere Systems Guardian Corp.

Reginald Conway Farrow

Isik C Kizilyalli

Gordon Albert Thomas

Alokik Kanwal

Nace Layadi

Zafar Iqbal

Sheng Liu

David M Boulin

Masis Mkrtchyan

Amit Goyal

Warren Kazmir Waskiewicz

Camelia Prodan

Arooj A Aslam

An imaging device and method of using is provided that requires no traditional optics but uses an addressable array of vertically oriented carbon nanotubes. The technique relies on the ability to reduce the nearest neighbor spacing between the carbon nanotubes to less than the wavelength of light used in traditional optical microscopes. The nanoscope can have a resolution of less than 100 nm. Electrophoresis deposition can be used to direct the assembly of the carbon nanotubes onto interconnects in an integrated circuit, which could be used to address the array. The device is portable, compact, and does not utilize complicated components. It also derives spatially resolved dielectric and chemical properties of a sample to be imaged.

Analytical nanoscope on a chip for sub-optical resolution imaging

Devices and methods for the measurement and control of fluid using one or two capacitors are described. The devices use Micro-Electro-Mechanical-Systems (MEMS) and radio-frequency inductive coupling to sense the properties of a fluid in a tube. The single and double capacitor devices may be coupled to shunts implantable in a patient and operable to be interrogated non-invasively. The shunts employing the novel capacitor devices are insensitive to stray signals such as the orientation of a patient's head. The devices are operable to employ a wireless external spectrometer to measure passive subcutaneous components.

Smart shunt devices and methods

A device for determining the presence of a single cell and/or determining a state of a single cell includes a first nanotube disposed on a first electrode, and a second nanotube disposed on a second electrode, wherein the first and second nanotubes are spaced apart at a length that is smaller than a cell size to be detected. A method for determining the presence of a single biological cell includes sensing impedance between a first nanotube and a second nanotube. A method of manufacturing includes providing a nanotube, providing an electrode coated with an insulating material, wherein an aperture is defined in the insulating material through to the electrode, and using electrophoresis deposition to deposit a nanotube within the aperture and in electrical communication with the electrode.

Nanoprobe and methods of use

A vibration-powered impact recording device that harvests power from vibrations that affect the device is provided. The recording device is affixed to an object and includes a vibration limit detection and recordation system. The system can include a suitable part that is fixed to the object, and a mass (or other suitable part) that is less firmly attached, with the relative motion between the two parts producing an electrical voltage. The electrical voltage can be used to power an information storage unit that records the details of the impact and optionally other sensors which record other parameters such as temperature, humidity etc. at the time of impact.

Vibration powered impact recorder (VPIR)

Improved nanotube devices and systems/methods for fabrication thereof are provided. The present disclosure provides systems/methods for depositing controlled numbers of nanotubes with specific properties at predefined locations for the fabrication of nanotube devices. The nanotube devices may be utilized in a range of applications. A bio-fuel cell system that does not require a proton exchange membrane separator and does not need a mediator to transfer charge is provided. This exemplary bio-fuel cell uses enzyme functionalized SWNTs for the anode/cathode. The absence of a membrane in the bio-fuel cell configuration opens up the possibility of other configurations that would otherwise be unfeasible. This includes a bio-fuel cell where the anode/cathode are on the same substrate. Since the electrodes can share the same substrate, the configuration may be integrated with a circuit device on the same substrate. An IC and its power source may be fabricated on the same silicon wafer.

System and method for directed self-assembly technique for the creation of carbon nanotube sensors and bio-fuel cells on single plane

A nanotube device and a method of depositing nanotubes for device fabrication are disclosed. The method relates to electrophoretic deposition of nanotubes, and allows a control of the number of deposited nanotubes and positioning within a defined region.

Nanotube device and method of fabrication

The present invention is an improved shunt system for draining CSF. The system includes a removable sheath for reduction of catheter clogging during shunt insertion, a catheter with relatively large holes, an extracranial filter to allow non-invasive filter replacement, and a wireless flow/pressure meter to monitor and control CSF flow.

No clog shunt using a compact fluid drag path

A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture. Embodiments of the present disclosure provide a method of depositing nanotubes in a region defined by an aperture, with control over the number of nanotubes to be deposited, as well as the pattern and spacing of nanotubes. For example, electrophoretic deposition, along with proper configuration of the aperture, allows at least one nanotube to be deposited in a target region with nanometer scale precision. Pre-sorting of nanotubes, e.g., according to their geometries or other properties, may be used in conjunction with embodiments of the present disclosure to facilitate fabrication of devices with specific performance requirements.

Method of forming nanotube vertical field effect transistor

A method and apparatus are disclosed for fabricating a substrate having a plurality of circuit patterns. The substrate is exposed to a primary mask having a plurality of the desired circuit patterns, surrounded by one or more exclusion regions, and a secondary mask having a pattern corresponding to the exclusion regions that satisfies at least one design rule for a subsequent process. The primary and secondary masks are exposed on the substrate in any order before the resist patterns are developed. The pattern on the secondary mask may comprise, for example, an array of fill patterns. The pattern on the secondary mask may satisfy design rules for more than one process level so that a single secondary mask can be utilized for multiple process levels. In addition, the substrate only needs to be exposed to the secondary mask for process levels where the exclusion regions violate a design rule.

Method and apparatus for manufacturing multiple circuit patterns using a multiple project mask

A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Multi-layered semiconductor structure

A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

Method of forming an alignment feature in or on a multi-layered semiconductor structure

Method of forming an alignment feature in or on a multilayered semiconductor structure

A process for device fabrication, including coating a wafer with a layer including SiO , SiN , and a first resist, defining shallow trench isolation and alignment patterns in the first resist, transferring the first resist pattern into the SiO and SiN , removing the first resist, etching trenches to a depth suitable for shallow trench isolation, coating the wafer with a second photoresist, defining open areas around alignment-marks, etching alignment mark trenches to a depth greater than the trench depth, suitable for alignment mark detection, removing the second resist and the SiN , depositing SiO to fill the trenches for shallow trench isolation and partially fill the alignment mark trenches for alignment mark detection; and performing chemical mechanical polishing, leaving shallow trench isolation features and topographical alignment marks. As a result, alignment marks can be fabricated from the STI level with an arbitrary depth and an SiO fill to produce topography and/or material contrast without accumulating errors by using a mask that is separate from the transistor isolation feature mask to define the alignment mark positions.

Growing community of inventors

Somerset, NJ, United States of America

Reginald Conway Farrow