International Business Machines Corporation

Reginald B Wilcox, Jr

Steven H Voldman

Albert John Wallash

William C Leipold

Daniel Nelson Maynard

David C Reynolds

Brian Douglas Pfeifer

Mitchell R DeHond

Gustavo Enrique Tellez

Philip S Honsinger

Bette L Bergman Reuter

Steven G Lovejoy

Charles L Meiley

Gary R Doyle

Gorden S Starkey

Betty L Bergman Reuter

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Physical design characterization system

A method for automatically wiring (i.e., routing) an integrated circuit chip after completing the placement of cells on the chip is described. The method employs a maze routing such that the spacing between the routed wires is increased, while at the same time maintaining control over the total wiring length. The maze routing herein described is modified to improve chip yield, reduce wiring capacitance, limit power consumption and coupled signal noise, all of which are achieved by increasing wire-to-wire spacings.

Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing

An MR head has its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to a silicon chip substrate ground potential or to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the wafer level to ultimate completion of individual sliders. At the wafer level a silicon wafer, which contains the integrated circuit devices, is fixedly mounted to a wafer of slider material, such as titanium carbide. A plurality of rows and columns of MR heads are constructed on the silicon wafer adjacent the integrated circuit devices. The composite wafer is then diced into quadrants wherein each quadrant contains rows and columns of sliders with MR heads. Each quadrant is then diced into rows. Each row is then diced into individual sliders, each slider carrying an MR head which is ESD protected.

Silicon chip with an integrated magnetoresistive head mounted on a slider

A process of making an MR head having its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the row level to ultimate completion of individual sliders. A silicon wafer, including the integrated circuit devices, is sliced into a plurality of silicon bars, each bar including a row of circuit devices. A plurality of rows and columns of MR heads are constructed on a ceramic wafer. The ceramic wafer is then also sliced into bars, each bar including a row of MR heads. Each silicon bar is then bonded to a ceramic bar, forming composite bars of MR heads electrically connected to the circuit devices. Each composite bar is then further processed and diced into individual sliders, each slider carrying an MR head which is ESD protected.

Process for manufacturing a silicon chip with an integrated

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Cambridge, VT, United States of America

Reginald B Wilcox, Jr