Advanced Micro Devices Corporation

Ati Technologies Ulc

Regina Tien Schmidt

Christopher A Spence

Richard Thomas Schultz

Marina V Plat

Khanh B Nguyen

Anna Maria Minvielle

Gladney Asada

Te-Hsuan Chen

Catherina Simona Matheis Ionescu

Chu-Wen Wang

Derek P Peterson

Elizabeth C Conrad

A system and method for fabricating on-die metal-insulator-metal capacitors capable of maintaining a similar capacitance for design reuse across multiple semiconductor fabrication processes are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. Subsequent semiconductor fabrication processes typically increase a number of metal plates that can be formed in the dielectric layer, such as an oxide layer, between two signal nets. To permit design reuse across multiple semiconductor fabrication processes, for a particular MIM capacitor designated to maintain a same capacitance, the additional metal plates for the particular MIM capacitor are formed as floating nets. Additionally, the same electrode plates of the particular MIM capacitor are used across the multiple semiconductor fabrication processes.

Method to create MIMcap designs across changing MIMcap structures

A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets such as two different power rails, two different control signals, or two different data signals. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. In high voltage regions, a MIM capacitor has one or more intermediate metal plates formed as floating plates between electrode metal plates. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit. The insulating distance between the two electrode metal plates includes the thicknesses of the two dielectric layers, but the thickness of the conductive floating metal plate does not contribute to this insulating distance.

High voltage tolerant capacitors

A system and method for detecting and measuring electrostatic discharge during semiconductor assembly are described. A semiconductor device fabrication process forms a conductor between two metal routes in a series path on a semiconductor die. The series path is between a bump on the die and a substrate tie. The two metal routes have a width greater than a threshold based on a metal width capable of conducting a critical current density caused by an electrostatic discharge event without conductive failure or breakdown. The conductor has a width less than the threshold. When an electrostatic discharge event occurs, if the current exceeds a critical amount of current, the conductor experiences conductive breakdown and current ceases to flow. During later testing, this series path is tested for open connections, which indicate whether the conductor acting as an electrical on-die fuse experienced conductive failure during assembly of a semiconductor chip.

Fuses to measure electrostatic discharge during die to substrate or package assembly

Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Power grid layout designs for integrated circuits

Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer. The film layer is etched to form a desired pattern of structures and implanted with a dopant to diffuse dopant atoms thoughout. Thereafter, critical dimension measurements of the structures are taken preferably using electrical line width measurements techniques. Variations in critical dimension measurements taken from the test wafer as compared to desired predetermined line width measurements are compensated for prior to manufacturing the final production wafer so as to provide circuits with the desired electrical parameters.

Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer

A method of determining at least one of focus and coma of a lens at a selected location in an imaging field, includes the step of forming a predetermined pattern on a mask for transference to a wafer through a lens. The pattern including a plurality of features such that a first of the plurality of features is situated adjacent a first side of a first phase shift region formed on the mask, and a second of the plurality of features is situated adjacent a second side of a second phase shift region formed on the mask, the second side being substantially opposite the first side. The method further includes the steps of transferring the pattern formed on the mask to the wafer, measuring a dimension of each of a first structure and a second structure formed on the wafer, the first structure being formed as a result of the first feature being transferred from the mask to the wafer and the second structure being formed as a result of the second feature being transferred from the mask to the wafer, and using the measured dimensions to determine the at least one of focus and coma of the lens at the selected location.

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Milpitas, CA, United States of America

Regina Tien Schmidt