Intel Corporation

Regev Shemy

Robert Valentine

Vinodh Gopal

Mark Jay Charney

Zeev Sperber

Rajesh Poornachandran

Wajdi K Feghali

Christopher J Hughes

Amit Gradstein

Alexander F Heinecke

Simon Rubanovich

Ittai Anati

Sean M Gulley

Menachem Adelman

Dan Baum

Jacob Doweck

Nilesh K Jain

Brinda Ganesh

Rinat Rappoport

Evangelos Georganas

Barukh Ziv

Jose Yallouz

Arik Narkis

Ilya Albrekht

Guy Boudoukh

Chitra Natarajan

Onkar P Desai

Yash Akhauri

Yaroslav Pollak

Igor Ermolaev

Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

Apparatuses, methods, and systems for hashing instructions

Integrated circuits to compute a result of summing m values, rotating the sum by k bits, and adding a summation of n values Bto Bto the rotated sum. An embodiment includes: a first carry save adder to add up the m values to generate a first carry and a first sum; rotator circuitry to rotate both the first carry and the first sum by k bits to generate a second carry and a second sum; a second carry save adder to add up the second carry, the second sum, and the summation of values Bto Bto generate a third carry and a third sum; two parallel adders to generate a first intermediate result and a second intermediary result based on the third carry and the third sum; and a multiplexer to generate the result utilizing various portions of the first and second intermediate results.

Efficient rotate adder for implementing cryptographic basic operations

Growing community of inventors

Kiryat Ata, Israel

Regev Shemy