Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Refael Ben-Rubi

Moshe Cohen

Mark Shlick

David Chaim Brief

Uri Shir

Ahiad Turgeman

Eran Sharon

Uri Peltz

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Data storage device that detects and releases bottlenecks in hardware

The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.

Data storage with real time dynamic clock frequency control

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in an input queue corresponding to a hardware module of a plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Data storage device that detects and releases input queue bottlenecks

The present disclosure generally relates to improved event filtering, debugging, and flow communication through a flow identifier. Rather than sending messages or events with no identity or with local identity (that is identity that has meaning only to a few modules, and not to all the modules), this disclosure suggests adding a flow identifier to each message or event. The flow identifier is at least two bits added to each message to be later identified when needed. A first message is sent to a HW or FW module. At either the HW or FW module an event will be generated. When the event is generated the flow identifier will be added to the event. The HW or FW module will then send the generated events along with the flow identifier to the TBRAM. Once received, the TBRAM will send the events along with the flow identifier to a PC.

Data storage device with flow tracking ability

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive read requests from a host device. When a read request is received corresponding to one or more pages from a first plane and one or more pages from a second plane, the controller is configured to determine a decode time for the pages of the first plane and the pages of the second plane. Based on the decode times for pages of the first plane and pages of the second page, pages of the first plane that have a similar decode time to pages of the second plane are read in parallel.

Data storage with improved read parallelism

The present disclosure generally relates to improving data transfer speed. A data storage device includes both a controller and a memory device. The controller provides instructions regarding read and/or write commands to the memory device through the use of control lines. The data to be written/read is transferred between the controller and the memory device along data lines. The control lines typically are not used during data transfer. During data transfer, the control lines can be used to increase data transfer speed by utilizing the otherwise idle control lines for data transfer in addition to the data lines. Hence, data transfer speed is increased by using not only the data lines, but additionally the control lines. Once the data transfer is complete, the control lines return to their legacy function.

Data storage with improved data transfer

A data storage device includes a memory device and a controller coupled to the memory device. When a program operation occurs, the controller is configured to determine a decode time for the data prior to programming the data to the memory device. The decode time determined by decoding the encoded data. A number of program loop cycles is determined using the decode time. The data is programmed to the memory device with the number of program loop cycles determined.

Data storage that controls decode performance by changing program PLC

The present disclosure generally relates to efficiently reading data during a suspend resume operation. Once writing is suspended, and prior to reading the data, a determination is made regarding whether there are multiple reads of the same page type. If there are multiple reads of the same page type, those reads are paired up so that the two reads of the same page type can occur from two planes in parallel. If two different pages types are read in parallel on the two planes, the slowest page type will determine the duration of the read. By grouping reads of the same page type and proceeding with the read, the disruption during suspend resume operations is minimized.

Data storage with improved suspend resume performance

The present disclosure generally relates to enhanced write performance by taking into consideration user write performance preferences as well as enhanced post write read (EPWR) scheduling. The user provides the write performance preferences to the data storage device. When a write operation happens, the data storage device checks the write performance preference for the current LBA as well as the write performance preference for the previous LBA. The data storage device will also check whether the current word line is scheduled for EPWR. Based upon the write performance preferences for the LBAs and the EPWR scheduling, the data can be written out of order to meet the user's write performance preferences. If the data is written out of order, the flash translation layer (FLT) is informed of the switch.

Data storage with improved write performance for preferred user data

Enhanced error correction for data stored in storage devices are presented herein. A storage controller retrieves an initial encoded data segment stored on a storage media, computes information relating to errors resultant from decoding the initial encoded data segment, and stores the information in a cache. The storage controller retrieves subsequent encoded data segments stored on the storage media, augments a decoder using at least the information retrieved from the cache, and decodes the subsequent encoded data with the decoder to produce resultant data.

Error correction decoding augmented with error tracking

An apparatus and method are described to determine line functionality between two electrical circuits to enable the line to run at a maximum frequency without deleterious conditions occurring from cross-talk effects.

Determining line functionality according to line quality in non-volatile storage

Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a memory module comprising non-volatile memory. Here, the memory module is configured to program a page of non-volatile memory with a first number of program cycles and indicate (e.g., to a host) that the page is partially programmed. The memory module is also configured to program the page with a second number of program cycles after a predetermined time, wherein the memory module performs one or more other storage operations during the predetermined time, and indicate (e.g., to the host) that the page is fully programmed.

Partial program operation of memory wordline

An apparatus includes one or more processors configured to execute instructions to generate a plurality of event results that includes a first event result and a second event result. The apparatus further includes a first buffer coupled to the one or more processors and a second buffer coupled to the first buffer. The first buffer is configured to store the plurality of event results. The apparatus further includes a circuit coupled to the first buffer. The first buffer is further configured to provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result.

Selective event logging

An apparatus includes an event message generator configured to generate an event message. The apparatus further includes a filter circuit configured to receive the event message and to send a first portion of the event message to a destination device. The filter circuit is further configured to selectively send a second portion of the event message to the destination device at least partially based on an event traffic load associated with the destination device.

Selective event filtering

Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data and a memory die comprising a plurality of non-volatile memory cells. Here, the memory die receives the threshold number of bit flips from the non-volatile storage controller, programs data to a set of the non-volatile memory cells over a first number of program loop cycles, and programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.

Growing community of inventors

Rosh-Ha′ayin, Israel

Refael Ben-Rubi