Cadence Design Systems, Inc.

Stmicroelectronics S.r.l.

Stmicroelectronics Gmbh

Reenee Raizada Tayal

Mayank Sharma

Vishal Agarwal

Gerard Tarroux

Jean-Noel Pic

Gianluca Blasi

Arnold Jean-Marie Gustave Ginetti

Sutirtha Kabir

Manav Khanna

Farhat Alam Khan

A computer may generate a record of a template associated with a schematic design corresponding to an integrated circuit design. The template may have one or more instances corresponding to one or more initial parameters associated with a chain of one or more transmission line components of the integrated circuit design. The computer may then modify content of the chain of one or more transmission line components in a circuit layout corresponding to the schematic design within the maximum range limit of the one or more initial parameters. The computer may update the one or more instances according to modified contents of the one or more transmission line components in the circuit layout.

Methods for layout driven synthesis of transmission line routes in integrated circuits

The present disclosure relates to a system and method for fluid parameterized cell (Pcell) evaluation. Embodiments may include displaying a fluid Pcell in a first format. Embodiments may further include identifying a first state in a fluid Pcell evaluation code. In some embodiments, the first state may indicate that alterations are being made to the fluid Pcell. Embodiments may also include displaying instances of the fluid Pcell in a second format based upon, at least in part, identifying the first state in the fluid Pcell evaluation code. Embodiments may further include identifying a second state in the fluid Pcell evaluation code. In some embodiments, the second state may indicate the completion of the alterations to the fluid Pcell. Embodiments may also include displaying a final instance of the fluid Pcell in the first format based upon, at least in part, identifying the second state in the fluid Pcell evaluation code.

System and method for fluid parameterized cell evaluation

A version management system for fluid guard ring (FGR) PCells uses one or more new version management parameters that are added to the FGR PCell definition to manage the source code versions for a PCell. The system saves instance layout information with a version management parameter that identifies the current PCell source code version for each FGR PCell instance. When evaluated using a newer version of the PCell source code, the instance layout information generated with a previous version of PCell source code can be retrieved. The retrieved layout information will be used during evaluation of the PCell to ensure the integrity of the PCell geometries that were previously verified. The saved layout information will be uniquely identifiable with a hash code of the name-value pairs for one or more parameters associated with the PCell instance.

Version management mechanism for fluid guard ring PCells

A computer based test bench generator () for verifying integrated circuits specified by models in a Hardware Description Language includes a repository () storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering behavior data () of an integrated circuit model (), and for entering configuration data () of the integrated circuit model. The generator automatically generates test benches () in the Hardware Description Language by making a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behavior data.

Test bench generator for integrated circuits, particularly memories

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Delhi, India

Reenee Raizada Tayal