Texas Instruments Corporation

Reed Wilburn Adams

Ross Eliot Teggatz

Suribhotla Rajasekhar

Sameer P Pendharkar

David John Baldwin

Amer H Atrash

Joseph A Devore

John H Carpenter, Jr

Thomas A Schmidt

William E Grose

Roland Bucksch

Suribhotla V Rajasekhar

A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and the drain of the first transistor; a bias source coupled to a control node of the switch such that the switch is ON during normal current mirror operation, and the switch is OFF during over voltage stress testing; and a clamp coupled between the control node of the switch and a source node.

Current mirror with circuitry that allows for over voltage stress testing

A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

Current limiting circuit for high-speed low-side driver outputs

A clamp for a FET switch utilizes a surge detector to turn off one of two bias circuits for the FET. The first biasing circuit provides the current necessary for high speed switching. The second biasing circuit provides a lower biasing current. A resistor or other device is used to allow the measurement of BVdss on the integrated circuit where the surge detector is connected from a terminal of the conductive path of the FET to the gate thereof. The switching circuit allows the surge detector to turn on the FET to act as a self-clamp when there is a spike in the voltage applied to the FET, such as when turning off an inductive load.

Clamping circuit for high-speed low-side driver outputs

The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure () that comprises a first transistor (), having a first terminal coupled to ground, a second terminal coupled to a control signal (), and a third terminal coupled to a first end of a first resistive element (). A first voltage source () is coupled to the second end of the first resistive element. A second resistive element () is intercoupled between the second end of the first resistive element and ground. A second transistor () has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (). A third resistive element () is intercoupled between the third terminal of the second transistor and ground; and a third transistor () has a first terminal coupled () to the oxide structure, a second terminal coupled to the first end of the first resistive elerment, and a third terminal coupled to a second voltage source ().

System for oxide stress testing

Disclosed are devices and associated methods for manufacturing an EEPROM memory cell ( ) for use on a negatively biased substrate ( ). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell ( ) including a DNwell ( ) formed on a P-type substrate ( ) for isolating the EEPROM cell ( ) from the underlying P-type substrate ( ).

Single-poly EEPROM on a negatively biased substrate

An integrated circuit ( ) having at least one programmable fuse (F ) and ESD circuitry (MN , MN ) preventing the fuse (F ) from being unintentionally blown when a voltage transient exists on a main voltage potential (V ). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MN ) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

Internal protection circuit and method for on chip programmable poly fuses

A variable transconductance current mirror circuit includes a first field effect transistor having a gate, a source, and a drain, and a second field effect transistor having a gate, a source, and a drain. The gate of the second transistor is coupled to the gate of the first transistor, and a current source is coupled to the gates of the first and second transistors. The circuit also includes a voltage supply coupled to the sources of the first and second transistors. The circuit further includes a first diode having an anode and a cathode. The anode of the first diode is coupled to the gates of the first and second transistors, and the cathode of the first diode is coupled to the source of the first and second transistors. The first diode comprises a zener diode having a reverse breakdown voltage operable to prevent gate oxide breakdown of the first and second transistors. The circuit may also include a second diode having an anode coupled to the drain of the first transistor, and a cathode coupled to the gates of the first and second transistors. The second diode is operable to vary the transconductance of the first and second transistors in response to changes in the current supplied to the drain of the first transistor.

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Plano, TX, United States of America

Reed Wilburn Adams