Evans & Sutherland Computer Corporation

Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Xilinx, Inc.

Reed P Tidwell

Steven Theodore Sprouse

James M Higgins

Rodney Brittner

Satish Babu Vasudeva

Jonathan Q Tu

Yoav Weinberg

Daniel Edward Tuers

Eran Erez

Matthew Davidson

Mark James Hardiman

Mark Hatch

David Wagner

Gary Pimentel

To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Power target calibration for controlling drive-to-drive performance variations in solid state drives (SSDs)

A non-volatile storage device comprises non-volatile memory cells, clocked circuity, and one or more control circuits. The one or more control circuits are configured to process commands to access the non-volatile memory cells using the clocked circuity, implement a power control loop to regulate power consumption of the non-volatile storage device based on a first feedback signal, implement a temperature control loop to regulate temperature of the non-volatile storage device based on a second feedback signal, and implement a clock frequency control loop to regulate one or more clock frequencies of the clocked circuitry based on a third feedback signal.

Integrated power and thermal management in non-volatile memory

In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

Distributed power management for non-volatile memory controllers

Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.

Reactive power management for non-volatile memory controllers

In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, receives power credits allocated by the storage controller, including an average power credit and a peak power credit; and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received average power credit and the received peak power credit. In some embodiments, a total number of average power credits allocated by the storage controller is variable and a total number of peak power credits allocated by the storage controller is fixed.

Distributed power management for non-volatile memory controllers using average and peak power credits allocated to memory channels

A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuitry may set or adjust the rates of variable-rate clock signals linearly in evenly-spaced increments and decrements.

Dynamic clock rate control for power reduction

A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuity may set or adjust the rates of variable-rate clock signals linearly in evenly-spaced increments and decrements.

In an apparatus for digital image processing, a mapper is coupled to receive destination pixel information in terms of a source pixel space, and to provide a 2-dimensional filter kernel with source pixels for the destination pixel information. An oversampled filter includes predetermined coefficients. A filter coefficient module is configured to select phase coefficients from the predetermined coefficients stored in the oversampled filter based on proximity to the source pixels in the filter kernel, and coupled to provide a filter coefficient for each of the source pixels in the filter kernel. A convolution module is coupled to receive the source pixels and the filter coefficients, and to provide a convolution result. The convolution module is configured to apply the filter coefficients to the source pixels in a convolution to provide the convolution result. A normalization module is configured to normalize either the convolution result or the filter coefficients.

Non-linear image mapping

In one approach for improving timing in an electronic circuit design having a finite state machine (FSM), control bit logic is generated based on next state logic of the FSM that generates current state bits of the FSM. The control bit logic and a control state bit are added to operate in parallel with the next state logic and the current state bit registers, and the output signal from the control bit register replaces selected logic in logic downstream from the FSM and current state bit registers. If a worst case delay is improved with the design having the control bit logic and control state bit, the modified circuit design is saved for evaluating other possible timing improvements. Otherwise, the modification is discarded.

Timing in a circuit design having finite state machines

An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The rational submultiple includes an integer part and a fractional part, the fractional part including a numerator and a denominator. A dithered pulse generator is configured to produce the dithered pulse signal from a count of the reference clock signal that is reset dependent on the integer part, and a fractional phase signal from a count that is incremented by the numerator and that is reset dependent on the denominator. A phase controller is configured to delay the dithered pulse with a delay proportional to the fractional phase to produce the output clock signal. The delay may be calibrated by internal logic.

Direct synthesis of audio clock from a video clock via phase interpolation of a dithered pulse

A method for communicating digital display data and associated auxiliary processing data from a frame buffer to a post processor. The method includes storing the display data and the auxiliary processing data in the frame buffer, forming video scan lines from the frame buffer by handling both the display data and the auxiliary processing data as video data, and transferring the video scan lines over a digital video interface to a post-processor.

System and method for communicating digital display data and auxiliary processing data within a computer graphics system

A method for is provided for antialiasing a computer graphics image using filtering. The method comprises the steps of defining a plurality of regions having samples from pixels in the computer graphics image, where the regions are associated with a pixel of interest and adjacent pixels to form an antialiasing filter. Another step is determining a contrast for each region. A further step is blending the regions that form the filter based on the contrast for each region.

System and method for auto-adjusting image filtering

A method for extending the data width of a graphics processing channel in a computer graphics system. The method includes the first step of providing a plurality of graphics processing channels having pre-defined output data widths or capacities. The next step is combining at least a portion of an output from at least two of the plurality of graphics processing channels. Another step is defining at least one extended graphics processing channel with an extended data width. The extended graphics processing channel is formed with output portions from the plurality of graphics processing channels.

Extended precision visual system

A method for using the alpha channel to generate screen space effects in a high fidelity, real time, computer graphics simulation system. The first step is providing a rendering engine with an alpha processing channel, a frame buffer that includes an alpha memory, and a post processor. Next, screen effect data is processed through the alpha channel. The third step is storing screen effect data in the alpha buffer memory. Then the screen effect data is applied to the frame buffer color data using the post processor. The primary screen effects that are desired to be generated through the alpha channel are double buffered overlays, accurate night scene rendering and edge blending attenuation at channel boundaries. Night scene rendering features include range attenuated slewable own-ship light lobes, non-attenuation of point lights and luminous polygons, and ambient lighting.

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Salt Lake City, UT, United States of America

Reed P Tidwell