Optimal Plus Ltd.

Optimaltest Ltd.

Intel Corporation

Reed Linde

Gil Balog

Avi Golan

Leonid Gurov

Alexander Chufarovsky

Gill Balog

Rich Fackenthal

Alec W Smidt

Sunil Gupta

Dan Glotter

A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.

System and method for binning at final test

Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Systems and methods for test time outlier detection and correction in integrated circuit testing

Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.

Misalignment indication decision system and method

Methods, systems, computer-program products and program-storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test-range. One method comprises: attaining results generated from a parametric test on semiconductor devices included in a control set; selecting from the semiconductor devices at least one extreme subset including at least one of a high-scoring subset and a low-scoring subset; plotting at least results of the at least one extreme subset; fitting a plurality of curves to a plurality of subsets of the results; extending the curves to the zero-probability axis for the low-scoring subset or the one-probability axis for the high-scoring subset to define a corresponding plurality of intersection points; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range.

System and methods for parametric testing

Methods for slow test time detection of an integrated circuit during parallel testing

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

Ultra low pin count interface for die testing

According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).

Growing community of inventors

El Dorado Hills, CA, United States of America

Reed Linde