Intel Corporation

Reed K Christensen

Robert W Martell

Andre E Wolper

A superscalar processor with a precise fault mechanism. Instructions are grouped into a cluster of instructions to be executed simultaneously by the superscalar processor. The cluster is formed from consecutively sequenced instructions according to a predetermined set of grouping rules. If at least one previously executed instruction exists, the consecutively sequenced instructions begin with an initial instruction that is the first instruction following a last previously executed instruction. Each instruction of the cluster is decoded and faulting instructions, if any, of the cluster are determined. Faulting instructions are instructions having an associated trace fault. If no faulting instructions were found, each instruction in the cluster is executed simultaneously. If, however, at least one faulting instruction was found, a break faulting instruction is determined. The break faulting instruction is the first faulting instruction in the consecutive sequence of the cluster instructions. The break faulting instruction and each instruction of the cluster in the consecutive instruction sequence prior to the break faulting instruction are then simultaneously executed.

Method and apparatus for providing precise fault tracing in a

A method and apparatus for providing trace fault information to a trace fault handler. The trace fault information is evaluated prior to beginning execution of a micro code flow. The evaluated trace fault information is stored in a buffer and the micro code flow is executed. While the micro code flow is executing, if a micro code instruction of the micro code flow is executed that enables tracing, the trace fault information stored in the buffer is written to a data storage area. The data storage area is accessible to the trace fault handler.

Trace event detection during trace enable transitions

A processor uses between-instruction in-circuit emulation breaks to implement complex in-circuit emulation features. The processor uses a bit in hardware that triggers a between-instruction break to in-circuit emulation to permit complex in-circuit emulation reactions such as break after processor reset or break on process switch.

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Hillsboro, OR, United States of America

Reed K Christensen