National Semiconductor Corporation

Eastman-kodak Company

Reda R Razouk

Michael P Brassington

Monir H El-Diwany

Mohamed N Darwish

Alexei Sadovnikov

Prateep Tuntasood

Peter B Johnson

Peter Smeys

Peter Deane

Gobi R Padmanabhan

Visvamohan Yegnashankaran

Waclaw C Koscielniak

Wipawan Yindeepol

Kulwant S Egan

Peter J Hopper

Michael E Thomas

Datong Chen

Abdalla Aly Naem

Jeffrey Robert Perry

Aaron Grant Simmons

Francois H&egrave;bert

Alexei Sadovinkov

Robert A Sabsowitz

Peter Johnson

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

Integrated circuit micro-module

An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode.

Optically-controlled shunt circuit for maximizing photovoltaic panel efficiency

A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.

Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure

An imaging cell and a method of forming the imaging cell are disclosed. The imaging cell includes a first transistor that has source, a drain, and a gate, and a second transistor that has a source, a drain, and a gate connected to the source of the first transistor. In addition, the cell has a photodiode that is partially formed over the source of the second transistor.

Color imager cell with transistors formed under the photodiodes

The drain-to-source field leakage current and the device-to-device field leakage current that are caused by radiation-induced hole trapping in the field oxide region are reduced in the present invention by forming the source and drain regions a distance apart from the edge of the field oxide region.

Radiation hardened MOS transistor

A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain regions. The side wall control gates can be used to substantially increase the threshold voltage of the transistor.

Deep submicron MOS transistor with increased threshold voltage

In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.

Small emitter and base-collector bi-polar transistor

A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor

A process for preparing a light-sensitive integrated circuit (IC) for packaging that provides a reduced exposure of the light-sensitive IC to light. The process includes providing a semiconductor substrate (e.g., a silicon wafer) with a plurality of light-sensitive ICs formed in/on its upper surface. The lower surface is optionally coated with opaque material. Next, the semiconductor substrate is diced to form individual light-sensitive ICs, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges. The semiconductor substrate lateral edges (and optionally backside) are then spray coated with an opaque material (e.g., opaque ink) to form an opaque layer covering the semiconductor substrate lateral edges. The opaque layer prevents light from entering the semiconductor substrate through the lateral edges and interfering with the operation of the light-sensitive IC. The inventive process is simple and inexpensive, employing, for example, piezoelectric injectors to spray coat opaque ink on the semiconductor substrate lateral edges as the individual ICs are conveyed through a pass-through. In addition, processes according to the present invention are independent of the techniques used to manufacture the light-sensitive ICs and, therefore, provide for increased packaging process flexibility and economy.

Method of preparing light-sensitive integrated circuits for packaging

A low-power high-frequency bipolar transistor is formed to have a small self-aligned intrinsic base region, and small self-aligned extrinsic base and emitter regions that contact the intrinsic base region. The small regions reduce the base resistance, the base-to-collector capacitance, and the base-to-emitter capacitance.

Polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and method of forming the transistor

A method of making high voltage complementary bipolar and BiCMOS devices on a common substrate. The bipolar devices are vertical NPN and PNP transistors having the same structure. The fabrication process utilizes trench isolation and thus is scalable. The process uses two epitaxial silicon layers to form the high voltage NPN collector, with the PNP collector formed from a p-well diffused into the two epitaxial layers. The collector contact resistance is minimized by the use of sinker up/down structures formed at the interface of the two epitaxial layers. The process minimizes the thermal budget and therefore the up diffusion of the NPN and PNP buried layers. This maximizes the breakdown voltage at the collector-emitter junction for a given epitaxial thickness. The epitaxial layers may be doped as required depending upon the specifications for the high voltage NPN device. The process is compatible with the fabrication of low voltage devices, which can be formed by placing the sinker regions under the emitter region. The thicknesses of the two epitaxial layers may be adjusted as required depending upon the specifications for the low voltage devices.

High-voltage complementary bipolar and BiCMOS technology using double expitaxial growth

A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.

Growing community of inventors

Sunnyvale, CA, United States of America

Reda R Razouk