Lawrence Livermore National Security, LLC

Other

University of California

Rebecca J Nikolic

Lars F Voss

Adam M Conway

Qinghui Shao

Sara Elizabeth Harrison

Stephen Anthony Payne

Robert T Graff

Clint Frye

Art J Nelson

John Winter Murphy

Erik Lars Swanberg, Jr

Roger A Henderson

Mark A Stoyer

Nerine Jane Cherepy

Chin Li Cheung

Catherine E Reinhardt

Dongxia Qu

Daniel Heineck

Joshua Jarrell

Joshua D Kuntz

Stephen E Sampayan

Srabanti Chowdhury

George James Caporaso

Mihail Bora

Hoang Tan Nguyen

Ishwara B Bhat

Hadong Kim

Cedric Rocha Leao

Sangtae Park

Daniel Max Dryden

Mushtaq A Dar

Patrick R Beck

Tzu Fang Wang

Victor P Karpenko

Dawn A Shaughnessy

Adam P Conway

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Three dimensional vertically structured electronic devices

A product includes a transparent scintillator material, a beta emitter material having an end-point energy of greater than 225 kiloelectron volts (keV), and a photovoltaic portion configured to convert light emitted by the scintillator material to electricity. A thickness the scintillator material is sufficient to protect the photovoltaic portion from significant radiation damage.

Indirect conversion nuclear battery using transparent scintillator material

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Liquid semiconductor-halogen based electronics

A product includes a transparent scintillator material, a beta emitter material having an end-point energy of greater than 225 kiloelectron volts (keV), and a photovoltaic portion configured to convert light emitted by the scintillator material to electricity.

According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Metal-based passivation-assisted plasma etching of III-v semiconductors

In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Gallidation assisted impurity doping

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Three dimensional vertically structured MISFET/MESFET

According to one embodiment, a product includes an array of three dimensional structures, where each of the three dimensional structure includes a semiconductor material; a cavity region between each of the three dimensional structures; and a first material in contact with at least one surface of each of the three dimensional structures, where the first material is configured to provide high energy particle and/or ray emissions.

Three dimensional radioisotope battery and methods of making the same

According to one embodiment, a product includes an array of three dimensional structures, a cavity region between each of the three dimensional structures, and a first material in contact with at least one surface of each of the three dimensional structures. In addition, each of the three dimensional structures includes a semiconductor material, where at least one dimension of each of the three dimensional structures is in a range of about 0.5 microns to about 10 microns. Moreover, the first material is configured to provide high energy particle and/or ray emissions.

Radiation tolerant microstructured three dimensional semiconductor structure

A photoconductive switch consisting of an optically actuated photoconductive material, e.g. a wide bandgap semiconductor such as SiC, situated between opposing electrodes. The electrodes are created using various methods in order to maximize reliability by reducing resistive heating, current concentrations and filamentation, and heating and ablation due to the light source. This is primarily accomplished by the configuration of the electrical contact geometry, choice of contacts metals, annealing, ion implantation, creation of recesses within the SiC, and the use of coatings to act as encapsulants and anti-reflective layers.

Reliable electrical contacts for high power photoconductive switches

In various approaches room-temperature gamma detector longevity may be improved by selectively removing, or selectively incorporating, alternate halogen component(s) from select surfaces of the detector. According to one embodiment, a method of improving operational longevity of a thallium bromide (TlBr)-based detector includes: selectively treating one or more surfaces of the TlBr-based detector to produce a surface substantially comprising pure TlBr. Similar techniques may be employed to restore a degraded or failed detector. According to another embodiment, a method of forming a TlBr-based detector exhibiting improved operational longevity includes: selectively treating one or more surfaces of the TlBr-based detector to replace Br therein with one or more alternate halogen components while also substantially avoiding replacing some or all of the Br in other surfaces of the TlBr-based detector with the one or more alternate halogen components. Corresponding structures for TlBr-based detectors with improved longevity are also described.

Selective surface treatment of thallium bromide (TLBR)-based detectors to improve longevity and/or restore operational capacity thereof

A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of &#x2dc;0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.

Growing community of inventors

Oakland, CA, United States of America

Rebecca J Nikolic