Advanced Micro Devices Corporation

Sun Microsystems, Inc.

Ambarella, Inc.

Reading G Maley

Amos Ben-Meir

Anil Mehta

Albrecht Schoy

Ting Yiu Tsui

Xiaojun Zhu

Sompur M Shivakumar

An apparatus comprising a transconductance control circuit, a boost control circuit, a current computation circuit and an oscillator circuit. The transconductance control circuit may be configured to generate a current control signal in response to (i) a voltage control signal and (ii) a plurality of range control signals. The boost control circuit may be configured to generate a current boost signal in response to a reference current signal and an enable signal. The current computation circuit may be configured to generate a first control signal and a second control signal in response to the current boost signal and the current control signal. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to the first control signal and the second control signal.

Temperature and/or voltage independent voltage controlled oscillator with programmable gain and/or output frequency range

An apparatus and a method are provided for generating a random number, wherein the randomness of the random number is derived from thermal noise present across a pair of resistors. Each of the pair of resistors is defined to receive a respective input voltage and add a respective noise component to the input voltage. The output from each resistor in the pair of resistors is amplified to generate a noisy analog voltage that includes a representation of the random noise components added by the pair of resistors. The randomly varying noisy analog voltage is used to control a voltage controlled oscillator (VCO). The VCO generates a random digital signal based on the randomly varying noisy analog voltage. The random digital signal generated by the VCO is used to set a number of bits for defining a random number.

Random number generation apparatus and method

A method and apparatus for compensating for tunneling leakage current through a first capacitor includes: an operational amplifier, connected in a negative feedback configuration; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The compensation capacitor is chosen so that the ratio of the area of the compensation capacitor divided by the area of the first capacitor is an area ratio &ldquo;AR&rdquo;. The operational amplifier sets the gate voltage of the compensation capacitor to be the same as the gate voltage of the first capacitor. The ratio of the size of the second compensation transistor divided by the size of the second compensation transistor is also the area ration &ldquo;AR&rdquo;. Consequently, the first compensation transistor and the second compensation transistor drain current out of the compensation capacitor and first capacitor, respectively, approximately equal to the amount tunneling leakage current through the compensation capacitor and first capacitor, respectively.

Method and apparatus for tunneling leakage current compensation

A flip-chip circuit arrangement having improved thermal management includes a base substrate having a top surface which includes one or more bond pads thereon. The arrangement further includes a semiconductor substrate having circuitry and one or more bond pads thereon, wherein the one or more bond pads on the semiconductor substrate correspond to the one or more bond pads on the base substrate. The semiconductor substrate has one or more channels which extend from a top surface to a bottom surface thereof and the channels facilitate a transfer of heat due to power dissipation of the circuitry away from the semiconductor substrate.

Stacked multi-chip modules using C4 interconnect technology having improved thermal management

A method of forming a test configuration for an integrated circuit employing a controlled, collapse chip connection technology to attach to another substrate is disclosed. The method includes the steps of forming one or more vias in a semiconductor substrate corresponding to the integrated circuit and forming circuitry on a top surface of the semiconductor substrate. The method further includes filling the one or more vias with a conductive material to form conductive channels through the semiconductor substrate which selectively couples to the circuitry to provide control signals thereto and receive output signals therefrom. One or more bond pads are formed on a bottom surface of the semiconductor substrate and correspond to the one or more conductive channels. The one or more bond pads on the bottom surface of the semiconductor substrate are coupled to bond pads on the another substrate using the controlled, collapse chip connection technique, which allows the top surface of the semiconductor substrate to be accessible for design verification or circuit test processes. The present invention further includes a controlled, collapse connection chip carrier system which includes a base substrate having one or more bond pads formed thereon and a circuit substrate having circuitry on a top surface thereof and one or more bonds pads on a bottom surface thereof which correspond generally to the one or more bond pads on the base substrate. The circuit substrate further includes one or more conductive channels extending therethrough which electrically couple selective portions of the circuitry on the top surface to the one or more bond pads on the bottom surface. The system further includes a controlled, collapse connection between the one or more bond pads on the base substrate and the one or more bond pads on the bottom surface of the circuit substrate which provides an electrical connection between the base substrate and selective portions of the circuitry on the top surface of the circuit substrate.

Bottom side C4 bumps for integrated circuits

There is provided a new polysilicon fuse structure for implementation within integrated circuit devices so as to permit programming of the same. The polysilicon fuse structure includes a first electrical contact region, a second electrical contact region, and multiple fuse regions interconnected between the first electrical contact region and the second electrical contact region. The multiple fuse regions are formed of a plurality of strips, each being of a different width and/or length, which are disposed in a spaced-apart relationship so as to form a small opening between adjacent strips. A number of the plurality of strips is selectively blown when a predetermined amount of current is passed from one of the first and second electrical contact regions through the plurality of strips to the other one of the first and second electrical contact regions so to limit the current passing to an integrated circuit device connected thereto during normal operating conditions.

Using polysilicon fuse for IC programming

An output buffer interfaces a digital system having devices designed for low operating voltages to an output coupled to an external system having higher operating voltages. The output buffer drives the output to one of a high output voltage and a low output voltage while limiting voltage across terminals of devices within the output buffer. The output buffer includes a pull-up stack of a first plurality of devices, coupled between a high power supply and the output, which turn on when the output is driven to the high output voltage and which turn off when the output is driven to the low output voltage. The voltage difference between the output and the high power supply is distributed across the first plurality of devices when the output is driven to the low output voltage. The output buffer further includes a pull-down stack of a second plurality of devices, coupled between a low power supply and the output, which turn on when the output is driven to the low output voltage and which turn off when the output is driven to the high output voltage. The voltage difference between the output and the low power supply is distributed across the second plurality of devices when the output is driven to the high output voltage. The output buffer further includes a clamping circuit, coupled to the output and to a predetermined node of the first and second plurality of devices, for limiting voltage across terminals of each of the first and second plurality of devices by discharging down the predetermined node when the output is driven to the low output voltage and by charging up the predetermined node when the output is driven to the high output voltage.

Output buffer with protective limit of voltage across terminals of

A level shifter interfaces a digital system having devices designed for low operating voltages to an external system having higher operating voltages. The level shifter is comprised of two level shifting stages. Each level shifting stage includes a pull-up stack of a plurality of pull-up devices, coupled between a high power supply and a coupling node, which turn on when the coupling node is driven to a high shifted voltage, which is substantially the voltage at the high power supply, and which turn off when the coupling node is driven to a low shifted voltage, which is substantially the voltage at a low power supply. Each level shifting stage further includes a pull-down stack of a plurality of pull-down devices, coupled between the low power supply and the coupling node, which turn on when the coupling node is driven to the low shifted voltage and which turn off when the coupling node is driven to the high shifted voltage. Each level shifting stage further includes a clamping circuit, coupled to the coupling node and to a predetermined node of the plurality of pull-up and pull-down devices, for limiting voltage across terminals of each of the plurality of pull-up and pull-down devices by discharging down the predetermined node when the coupling node is driven to the low shifted voltage and by charging up the predetermined node when the coupling node is driven to the high shifted voltage. Thus, the level shifter shifts a lower core voltage range from the digital system to a higher shifted voltage range of the external system while limiting voltage across terminals of devices within the level shifter to prevent device breakdown and degradation.

Level shifter with protective limit of voltage across terminals of

A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.

Processor with short set-up and hold times for bus signals

An improved gate oxide protected level shifter is provided which has a higher speed of operation than is traditionally available. The level shifter includes a first capacitor coupled between a first output terminal and the input of an inverter and a second capacitor coupled between a first node and the output of the inverter. As a result, the speed of the transitions at the gates of the pair of cross-coupled P-channel MOS transistors is increased several times.

High speed gate oxide protected level shifter

A reference voltage generation circuit is provided for use in gate oxide protected circuits for generating an NMOS reference voltage and PMOS reference voltage in which the NMOS reference voltage is independent of an I/O buffer power supply potential and in which the PMOS reference voltage tracks the supply voltage. The reference voltage generation circuit includes a bandgap voltage reference circuit, a first operational amplifier, a voltage divider and a second operational amplifier. In one embodiment, the NMOS reference voltage is approximately +2.2 volts and is referenced with respect to ground. The PMOS reference voltage is approximately +1.1 volts and referenced with respect to the I/O buffer power supply voltage and the NMOS reference voltage.

Reference voltage generation scheme for gate oxide protected circuits

A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.

Cross clock domain clocking for a system using two clock frequencies

An oxide protection circuit prevents failure of the MOS transistors in a digital device. A voltage difference at a gate oxide of a digital device does not exceed a breakdown voltage magnitude. The gate oxide protection circuit includes a plurality of transistors which turn OFF or ON when a node reaches a predetermined voltage of V.sub.refp +V.sub.t or V.sub.refn -V.sub.t, where V.sub.refp and V.sub.refn are reference applied at a gate of a PMOS or an NMOS transistor, and V.sub.t equals a threshold voltage of the MOS transistor.

Growing community of inventors

San Francisco, CA, United States of America

Reading G Maley