International Business Machines Corporation

Razvan Peter Figuli

Cedric Lichtenau

Stefan Payer

Kerstin Claudia Schelm

Michael Klein

Nicol Hofmann

Eric M Schwarz

Jonathan D Bradbury

Silvia Melitta Mueller

Petra Leber

Dung Q Nguyen

Vijayalakshmi Srinivasan

Kailash Gopalakrishnan

Maarten Jakob Boersma

Wei Wang

Swagath Venkataramani

Yulong Li

Preetham M Lobo

Michael Klaus Kroener

Sunil K Shukla

Niels Fricke

Holger Horbach

Puja Sethia

Martin A Lutz

Nandor Szirmak

Revital Arieli

Eric Mark Schwarz

Processing input data for transmittal to a data consumer such as an artificial intelligence engine is performed by arranging the input data into a uniform structure made up of sticks of data combined to form pages of sticks. A stick is any well-sized set of input data elements whereby the size of the stick is fixed. A masking pattern is established for sticks of data having certain ranges of invalid data for consumption of partial sticks while maintaining validity of the input data being transferred. The mask pattern is derived based on set-active-mask-and-value (SAMV) instructions. The derived mask pattern is carried forward for subsequent load instructions to the data consumer.

Padding input data for artificial intelligence accelerators

A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.

Variable replacement by an artificial intelligence accelerator

An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

Vector string search instruction

Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

Parallel rounding for conversion from binary floating point to binary coded decimal

A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

Parallelized rounding for decimal floating point to binary coded decimal conversion

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

Residue checking of entire normalizer output of an extended result

A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

Fault-tolerant clock gating

A method for detecting faults in substring search operations includes providing, using a processor unit including vector registers of M vector elements each, an M&#xd7;M matrix of comparators for characterwise comparison of the elements of a reference string stored in a first one of the vector registers and a target string stored in a second one of the vector registers. A vector element is an n-bit element for encoding a character. A resulting bit vector is generated using comparison performed by the M&#xd7;M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicates characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by utilizing the resulting bit vector.

Plausability-driven fault detection in result logic and condition codes for fast exact substring match

A method for detecting faults in substring search operations using a processor unit including vector registers of M vector elements each. A non-limiting example of the method includes providing an M&#xd7;M matrix of comparators for characterwise comparison of the elements of a reference string and a target string. A first zero detect vector having value indicative of terminating element of the target string and a second zero detect vector having a value indicative of terminating element of the reference string are generated. A resulting bit vector is generated using comparison performed by the M&#xd7;M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicate characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by comparing the generated zero detect vectors with operands.

Plausibility-driven fault detection in string termination logic for fast exact substring match

The present disclosure relates to a method to execute successive dependent instructions from an instruction stream in a processor. In an embodiment, the invention relates to a method to execute successive dependent instructions from an instruction stream in a processor. The method may include identifying a first instruction and a second instruction. A given operand of a second instruction is an output of the first instruction of the pair. The first instruction is older than the second instruction. The method may include loading the operands of the first instruction and the second instruction. The method may include executing the first instruction and the second instruction.

Method to execute successive dependent instructions from an instruction stream in a processor

A substring can be detected within a string of data elements through a method that includes partitioning and distributing the string of data elements to an ordered list of segments having equal lengths greater than or equal to the length of the substring. A substring match within a segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. A carry vector that includes the substring match can be created, in response to detecting the substring match that is a partial match. It can be determined that a carry vector exists by comparing the substring with the segment of the ordered list of segments, and it can be subsequently determined that a full match exists between the carry vector and the segment of the ordered list of segments.

Rapid substring detection within a data element string

A processor unit can rapidly search a string of characters. The processor unit includes vector registers each having M vector elements, each having n bits of data for containing an encoded character. An M&#xd7;M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each upper diagonal of the matrix of comparators and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. The processor unit result generating logic generates, using the resulting bit vector, an indication of a substring of the target string that matches a fragment of the reference string.

Rapid partial substring matching

A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L&#x2212;1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.

Non-overlapping substring detection within a data element string

A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M&#xd7;M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.

Growing community of inventors

Remchingen, Germany

Razvan Peter Figuli