Intel Corporation

Razi Uddin

Chee How Lim

Usman Mughal

Songmin Kim

Steven A Peterson

Gregory F Taylor

Anthony Babella

Kapila B Udawatta

Steve A Peterson

Raghu P Raman

Vishal Sharma

A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.

Method and apparatus for generating multiple system memory drive strengths

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is shifted to generate a slave impedance code. The slave impedance code is provided to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation.

Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation

A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.

Method and apparatus to enhance testability of logic coupled to IO buffers

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is provided (as a slave impedance code) to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation. Using the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs.

In a system, such as an open-drain bus architecture system, a termination impedance can be dynamically coupled or de-coupled from a bus. The termination impedance is coupled to the bus by a dynamic control circuit if a signal is being received from the bus or if a binary 1 is driven on the bus. The termination impedance is de-coupled from the bus by the dynamic control circuit if a binary 0 is driven on the bus. Coupling the termination impedance to the bus improves signal quality by providing a matching impedance. De-coupling the termination impedance reduces power dissipation and improves receiver noise margin.

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Orangevale, CA, United States of America

Razi Uddin