Stmicroelectronics Gmbh

Qualcomm Incorporated

St-ericsson Sa

Razak Hossain

Hasnain Lakdawala

Marco Zanuso

Masoud Moslehi Bajestan

Bernard Bourgin

Thomas David Zounes

Fabrizio Viglione

Scott B Anderson

Lun Bin Huang

Andras Pozsgay

Marco Cavalli

An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

Frequency doubler with duty cycle correction

An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

Calibration of sampling-based multiplying delay-locked loop (MDLL)

A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

Scan chain modification for reduced leakage

A parallel, multi-stage noise shaping (MASH) delta-sigma (&#x394;&#x3a3;) modulator reduces the required operating frequency by predicting the inputs to later stages of a serial MASH modulator to be multiples of the MASH input. An Nth order parallel MASH &#x394;&#x3a3; modulator generates N outputs (one from each stage) in a single modulator cycle. Accordingly, the Nth order parallel MASH &#x394;&#x3a3; modulator may be operated at 1/N the frequency of a corresponding prior art Nth order serial MASH &#x394;&#x3a3; modulator.

Parallel mash &#x394;&#x3a3; modulator

In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Crosstalk noise reduction circuit and method

A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.

Domino logic compatible scannable flip-flop

A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design.

Method for synthesizing domino logic circuits cross reference to related patent application using partition

A method for synthesizing a domino logic circuit design () from a source circuit definition () using a static logic circuit synthesis tool () includes generating a preliminary domino logic circuit () design using the circuit synthesis tool () and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design ().

Method for synthesizing domino logic circuits

A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Pulse triggered static flip-flop having scan test

A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

System and method for predictive comparator following addition

There is disclosed a circuit for determining the number of Logic 1 bits in a group of N data bits. The circuit comprises: 1) an input stage of 4:3 carry-save adders, each of the 4:3 carry-save adders receiving four of the N data bits on four input lines and generating three sum bits (S , S , S ) equal to a total number of Logic 1 bits on the four input lines, wherein the three sum bits have bit weights of S &equals;4, S &equals;2 and S &equals;1, respectively; 2) a first intermediate stage of 4:2 carry-save adders, each of the first intermediate stage 4:2 carry-save adders having four input lines for receiving selected ones of the S sum bits, the S sum bits, and the S sum bits and generating therefrom a carry-out (COUT) bit, a carry (C) bit and a sum (S) bit; and 3) a carry-propagate adder having a first input channel and a second input channel coupled to the first intermediate stage 4:2 carry-save adders and capable of generating a binary result equal to a total number of Logic 1 bits in the group of N data bits.

Circuit for determining the number of logical one values on a data bus

There is disclosed a circuit for determining if an N-bit number is equal to a power of two. The circuit comprises: 1) a first stage of detection gates, each of the first stage detection gates capable of receiving a first data bit and a second data bit from the N-bit number and generating a first output bit and a second output bit, wherein the first and second output bits are 01 if the first and second data bits are different and are one of 00 and 11 if the first and second data bits are the same; and 2) a second stage of detection gates coupled to the outputs of the first stage of detection gates, each of the second stage detection gates receiving three of the first stage output bits and generating a first output bit and a second output bit, wherein the first and second output bits of the second stage detection gates are 01 if only one of the three first stage output bits is equal to Logic 1 and are one of 00 and 11 otherwise.

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San Diego, CA, United States of America

Razak Hossain