International Business Machines Corporation

Raymond Wong

Michael James Becht

Jeffrey M Turner

Nihad Hadzic

Michael J Cadigan, Jr

Jie Zheng

Carl Alfred Bender

Howard M Haynie

Mushfiq U Saleheen

Clinton E Bubb

Jeffrey C Hanscom

Ying-Yeung Li

Andreas Kohler

Yuen C Tschang

Christine Soong

Michael J Cardigan, Jr

Aspects of the invention include receiving a request for data. The request is received from a computing element implementing a first bus protocol, and the data is accessible via a reduced instruction set computer (RISC) system implementing a plurality of bus protocols. A type of the received request is determined. A bus protocol is selected from the plurality of bus protocols based at least in part on the type of the received request. The received request is translated into a format that is compatible with the selected bus protocol and transmitted to the RISC system. Data is received from the RISC system in response to transmitting the translated request.

Substitution through protocol to protocol translation

Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.

Array clocking in emulation

Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

Predictive caching for check word snooping in high performance ficon

Examples of techniques for hang detection and recovery are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: sending, by a processor, a read request to a controller; detecting, by a data hang detection circuit, the read request; initiating, by the data hang detection circuit, a counter when the read request is first detected; monitoring, by the data hang detection circuit, to receive a read response from the controller; and responsive to the counter reaching a timeout threshold before receiving the read response, sending, by the data hang detection circuit a timeout error to the processor via a multiplexer in the data hang detection circuit.

Hang detection and recovery

Predictive caching for check word snooping in high performance FICON

Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.

Transparent north port recovery

A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.

Checksum calculation, prediction and validation

A computer-implemented method that includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

Memory saving packet modification

The method includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. A computer program product for directing a computer processor to perform a method. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.

Growing community of inventors

Hopewell Junction, NY, United States of America

Raymond Wong