Advanced Micro Devices Corporation

Raymond T Lee

Asim A Selcuk

Stephen C Horne

John Christian Holst

Nicholas John Kepler

Richard K Klein

Christopher A Spence

Zicheng Gary Ling

Craig S Sander

Todd P Lukanc

Robin W Cheung

Richard J Huang

William George En

Darin A Chan

Rich K Klein

Rajat Rakkhit

Christoper A Spence

Minh Van Ngo

Fei Wang

Paul Raymond Besser

Christopher F Lyons

Matthew S Buynoski

Sunil D Mehta

David Keating Foote

Khanh Q Tran

Susan H Chen

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Minimizing transistor size in integrated circuits

CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.

Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers

Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed on the substrate. A layer of a conductive material, such as polysilicon, is formed on the gate oxide layer, masked and etched to form an extended-width gate having endcaps of a greater width than the endcap design rules. A second mask is formed to cover the extended-width gate up to the desired width of the endcaps (i.e., the design width) and to expose the portions of the extended-width gate beyond the endcap design width. The exposed portions of the extended-width gate are then etched, resulting in a completed gate having endcaps of the design width. Since the endcaps are initially formed to a greater width than the design width, any pullback that occurs during printing of the mask or etching of the gate does not cause the gate to be insufficiently wide to avoid source/drain leakage. Since the excess endcap material is removed, adjacent features and/or devices can be densely spaced on the substrate.

Two step mask process to eliminate gate end cap shortening

MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable aluminum sidewall spacers, which can be easily formed and removed without damage to other structures on the substrate or to the substrate silicon, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

Aluminum disposable spacer to reduce mask count in CMOS transistor formation

Semiconductor devices of different conductivity types with optimized junction locations are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, sidewall spacers on side surfaces of the gates, and nitride disposable spacers on the sidewall spacers. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the nitride disposable spacers on the sidewall spacers on the unmasked gates removed, and lightly or moderately doped source/drain extension implants of the second impurity type formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining nitride disposable spacers removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using nitride disposable spacers, the critical masking steps for source/drain ion implantation are reduced to two, thereby reducing production costs and increasing manufacturing throughput. By employing sidewall spacers, impurities are prevented from being implanted at the edges of the gates. Thus, when source/drain junctions are formed, as by heating and diffusing the implanted impurities, they are advantageously located proximal to the gate edges, and not under the gates, thereby improving device performance.

Nitride disposable spacer to reduce mask count in CMOS transistor formation

Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable amorphous silicon spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable spacers, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation

A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Forming minimal size spaces in integrated circuit conductive lines

A semiconductor device having at least a first and second type of devices formed in the substrate of the semiconductor device and having a hydrogen free barrier layer formed by implanting nitrogen into a layer of amorphous silicon or polysilicon formed on the surface of the semiconductor device. A hydrogen getter layer is formed on the semiconductor device under the barrier layer. The hydrogen getter layer is removed from portions of the semiconductor device on which salicide layers are to be formed.

Formation of a barrier layer for tungsten damascene interconnects by

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.

A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.

Multipurpose cap layer dielectric

Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable nitride spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable spacers, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

Nitride disposable spacer to reduce mask count in CMOS transistor

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.

Forming local interconnects in integrated circuits

A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

Method for self-aligning polysilicon gates with field isolation and the

A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

Growing community of inventors

Sunnyvale, CA, United States of America

Raymond T Lee