Amazon Technologies, Inc.

Raymond Scott Whiteside

Thomas A Volpe

Ron Diamant

Kun Xu

Ilya Minkin

Declan Conlon

Nafea Bshara

Mohammad El-Shabani

Uday Shilton Udayaselvam

A technique for processing strong ordered transactions in a direct memory access engine may include retrieving a memory descriptor to perform a strong ordered transaction, and delaying the strong ordered transaction until pending write transactions associated with previous memory descriptors retrieved prior to the memory descriptor are complete. Subsequent transactions associated with memory descriptors following the memory descriptor are allowed to be issued while waiting for the pending write transactions to complete. Upon completion of the pending write transactions, the strong ordered transaction is performed.

Strong ordered transaction for DMA transfers

Techniques to reduce overhead in a direct memory access (DMA) engine can include processing descriptors from a descriptor queue to obtain a striding configuration to generate tensorized memory descriptors. The striding configuration can include, for each striding dimension, a stride and a repetition number indicating a number of times to repeat striding in the corresponding striding dimension. One or more sets of tensorized memory descriptors can be generated based on the striding configuration. Data transfers are then performed based on the generated tensorized memory descriptors.

Multidimensional and multiblock tensorized direct memory access descriptors

Techniques to reduce the latency in notifying that space in a memory has been freed up are described. For example, when moving data from on-chip memory of a computing engine to system memory, the computing engine can be notified that its on-chip memory is free before an acknowledgment is provided by the system memory that the data being moved has been written into the system memory. The computing engine can be given access to the on-chip memory sooner by generating an early semaphore update based on a determination that the set of data being moved to system memory has been read out from the on-chip memory. The early semaphore update need not wait for the acknowledgement from the system memory, thus reducing the latency of notifying the computing engine that the on-chip memory is free.

Early semaphore update

To reduce direct memory access (DMA) overhead, a tensorized descriptor can be used to generate a series of memory descriptors to perform a series of DMA data transfers. The tensorized descriptor may include attributes such as a stride and a memory descriptor template, which can be used to generate the series of memory descriptors. Hence, instead of having to retrieve each of the memory descriptors to perform the series of DMA transfers, a single tensorized descriptor can be retrieved to perform a series of data transfers.

Tensorized direct memory access descriptors

An integrated circuit configured to execute program instructions can generate, based on a configuration, any combination of a notification message, a halt signal, or an interrupt signal for a condition detected in the integrated circuit. The detected condition can be an error condition or a non-error condition. The notification message for the condition may be written to memory accessible by a host processor. The non-error condition may be used by the host processor to monitor internal states of the integrated circuit. The halt signal may be used to stop the integrated circuit from executing the instructions.

Configurable reporting for device conditions

Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, an integrated circuit device can be operable to determine, at a point in time during operation of the integrated circuit device, to generate a notification. The notification can include a type and a timestamp indicating the point in time. The notification can also include information about an internal status of the integrated circuit at the point in time. The device can further selectin a queue from a plurality of queues in a processor memory of the computing system that includes the integrated circuit. The device can further generate a write transaction including the notification, where the write transaction is addressed to the queue. The device can further output the write transaction using a communication interface of the device.

Notifications in integrated circuits

Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, an integrated circuit device can include a memory for storing instructions a configuration register, and an instruction execution circuit. An instruction read from the memory can be a reconfigurable instruction. which includes a set of fields corresponding to a plurality of operations. Values in the fields can determine whether the operations are enabled or disabled. For example, a first value in a first field can enable a first operation. Whether the first operation is performed can further be determined by comparing a second value in a second field to a third value read from the configuration register. The value set in the configuration register thus can control whether the operation is performed.

Reconfigurable instruction

Provided are systems and methods for managing historically large flows in network visibility monitoring. In some implementations, provided is an integrated circuit. The integrated circuit may be operable to receive packet information describing a packet at the cycle of a clock input. The packet may be associated with a packet flow being transmitted across a network. The integrated circuit may further generate keys using information identifying a packet flow provided by the packet information. The integrated circuit may further read values for counters and state information associated with each counter from a memory, using the keys. The integrated circuit may further determine from the state information that the packet flow identified by the packet information is a historically large packet flow. Upon determining that the packet flow is a historically large packet flow, the integrated circuit may further update an entry in a flow memory using the packet information.

Counters for large flow detection

Provided are systems and methods, including an integrated circuit, for data decompression of data encoded using a fixed-length encoding technique. For a data set where some symbols appear more frequently than others, the frequent symbols can be encoded into a short encoded symbol, and the remaining symbols can be encoded into a long encoded symbol. A decompression circuit can include decoder circuits that, upon receiving a set of input bits, can determine whether the set of input bits include one long encoded symbol or one or more short encoded symbols. The decoder circuit can then decode the one long encoded symbol or the one or more short encoded symbol. The fixed length of the encoded symbols can enable the decompression circuit to output decoded symbols at a same rate at which the circuit receives encoded symbols.

Decompression circuit

Provided are systems and methods for sampling packets based on large flow detection, for network visibility monitoring. In some implementations, provided is an integrated circuit. The integrated circuit may include large-flow detection logic and a sampling determination logic. The integrated circuit may be operable to received packet information describing a packet a cycle of a clock input. The packet may be associated with a packet flow being transmitted through a network. The integrated circuit may further be operable to determine, using the large-flow detection logic, whether the packet is associated with a large packet flow or a small packet flow. Upon determining that the packet is associated with a small packet flow, the integrated circuit may update the sampling determination logic.

Sampling based on large flow detection for network visibility monitoring

Historically large flows in network visibility monitoring

Provided are systems and methods for network visibility monitoring. In some implementation, provided is an integrated circuit. The integrated circuit may include a large-flow detection logic operable to determine whether a packet is associated with a large packet flow or a small packet flow, a large-flow caching logic operable to store information about packet flows, a sampling logic operable to sample packets, and a unique-flow estimation logic. The integrated circuit may be operable to receive packets from a network during a pre-determined interval, The integrated circuit may further determine an estimate of the number of unique flows represented by the packets, identify large packet flows by identifying packets associated with the large packet flows, store information about the large packet flows, determine packets associated with small packet flows, and sample the packets determined to be associated with the small packet flows to create packet samples.

Network visibility monitoring

Provided are systems and methods for large flow detection for network visibility monitoring. In some implementations, provided is an integrated circuit. The integrated circuit may be operable to receive packet information describing a packet at a cycle of a clock input. The packet may be associated with a packet flow being transmitted across a network. The integrated circuit may further generate a key using information identifying the packet flow provided by the packet information. The integrated circuit may further read a value for a counter from a counter memory using the key. The integrated circuit may determine whether the packet is associated with a large flow or a small flow using the counter and a packet size provided by the packet information. Upon determining that the packet is associated with a large flow, the integrated circuit may update an entry in a flow memory using the packet information.

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Austin, TX, United States of America

Raymond Scott Whiteside