Intel Corporation

Ampere Computing LLC

Raymond Scott Tetrick

Blaise B Fanning

Shekoufeh Qawami

Frank T Hady

Mark A Schmisseur

Robert J Royer, Jr

David B Minturn

Shane Matthews

Robert L Farrell

Ram Huggahalli

Alireza Sarabi

Robert G Blankenship

David I Poisner

Robert J Greiner

Shivnandan D Kaushik

David Lawrence Hill

Herbert H J Hum

Frank Binns

Nagi Aboulenein

Keshavan K Tiruvallur

Dale J Juenemann

Massimo Sutera

Ramakrishna Huggahalli

Brannon J Batson

Steven D Kassel

Robert J Brennan

Edwin L Jacks, Jr

Sudarshan Balachandran

John Beaston

Disclosed are techniques for memory resource control using Memory System Resource Partitioning and Monitoring (MPAM). In an aspect, a method of memory-system resource usage monitoring on a processing unit may include attaching a partition identifier from a set of partition identifiers to each memory access request of a plurality of memory access requests on an interconnect. The method may also include interleaving each memory access request of the plurality of memory access requests to a set of memory system components. The method may also include determining a first bandwidth associated with a first memory system component of the set of memory system components. The method may also include applying the first bandwidth associated with the first memory system component to one or more other memory system components of the set of memory system components based at least in part on the interleaving each memory access request.

Techniques for memory resource control using memory resource partitioning and monitoring

Disclosed are techniques for a processing device including a mesh network connecting at least a request node device, multiple home node devices, and multiple slave node devices. In an aspect, the request node device may select a target home node device. The home node devices may be divided into M groups of home node devices. The request may be routed from the request node device to the target home node device. The target home node device may select a target slave node device from a target group of M groups of slave node devices associated with a target group of the M groups of home node devices to which the target home node device belongs. The request may be routed from the target home node device to the target slave node device.

Apparatus and method of routing a request in a mesh network

Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Techniques to configure a solid state drive to operate in a storage mode or a memory mode

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Multi-level memory with direct access

Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

Apparatus and method for multi-level cache utilization

Architectures and techniques that allow legacy pin functionality to be replaced with a 'virtual wire' that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Virtualization of pin functionality in a point-to-point interface

According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.

Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system

An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.

Method and apparatus for initiating CPU data prefetches by an external agent

Growing community of inventors

Portland, OR, United States of America

Raymond Scott Tetrick