Lucent Technologies Inc.

Alcatel-lucent USA Inc.

Ascend Communications, Inc.

Raymond Schmidt

John Patrick Jones

Thomas Andrew Hoch

Prasasth Reddy Palnati

Andrew A Long

Ronald Mark Parker

P K Chidambaran

Mahesh N Ganmukhi

Brian Branscomb

Patrick L DeAngelis

Frank K Bradbury

Douglas MacIntyre

Eric L Reed

Scott Whitney

Synchronous timing techniques provide redundant reference frequencies to enable a packet switching system to continuously generate one or more master clock frequencies when an original reference frequency is lost or unavailable.

Methods and devices for synchronizing the timing of logic cards in a packet switching system without data loss

A methodology is provided for fault detection and service restoration in a multiservice switch on a per flow basis. An ingress source transmits the same data over each of two redundant cores. An egress receiver selects on a per flow bass which core to utilize. Bi-directional flows are not necessarily grouped together. The basic approach to fault detection is to assume that the two cores are not in lock step, but that the shelves are continually monitoring link flows for control path data as well as user data. The path monitoring is accomplished using a combination of arbiter and aggregator functions found in the service shelves and core interface cards, respectively. The arbiter transmits link test cells to both cores on a per flow basis, wherein the link test cells traverse and are monitored by respective aggregators to and from each core. When an egress arbiter determines that a flow is bad, it initiates a switch to the alternative source core, from which the flow would continue.

Apparatus and method for flow path based fault detection and service restoration in a packet based switching system

The present invention is a methodology for controlled switchover of unicast and multicast data flows in packet based switching system. In some cases it is advantageous to purposefully support switchover of flows from one path to the other without causing loss of data. This is termed a 'controlled' or 'hitless' switchover. In accordance with the present invention switchover methodology, given that an ingress arbiter device is transmitting to both cores simultaneously, it is required that the flows to both switching cores be synchronized at an aggregator level and that an egress arbiter be given time to cease receiving packets from one Core then switch over to the other Core, and continue receiving packets.

Controlled switchover of unicast and multicast data flows in a packet based switching system

The present invention is a core interface mechanism that permits 1:N type port protection on the core side of the switch such that core bandwidth is not wasted by the direct connection of service cards to the switching core. In an exemplary embodiment, a core interface module supports up to two active service cards and one dedicated protection service card. To provide increased efficiency and lower cost the redundant service card does not strand user bandwidth in the switch core. In an exemplary embodiment, the core interface includes a plurality of core side input and output ports for coupling to the switching core and a plurality of card side input and output ports for coupling to the service cards. A data flow switch function couples between the core side ports and the card side ports. The data flow switch function operates to complete data flow paths between the core side ports and the card side ports. A link failure detector detects a communications failure on a communications link associated with one of the active service cards and alters the data flow switch function such that one or more of said data flow paths associated with one of the active service cards are switched to one of said protection cards. The bandwidth allotment between the service cards and the interface device is generally greater than available bandwidth between the switching core and the interface device, thereby enabling connection of the protection cards without corresponding usage of switching core bandwidth.

Apparatus and method for redundancy of processing modules interfaced to a switching core

A data communications switch and method of operation are presently disclosed enabling flexible, selectable provision of a common timing signal for synchronized external communication through physical layer interfaces with other network devices, synchronized internal communications within the switch, and for uninterrupted synchronization of such communications. Synchronization of external communications is enabled by programmable selection from among plural potential timing references at redundant timing modules (TMs). An active TM provides a primary external synchronization clock; a standby TM provides a redundant timing function. Both TMs access the same references. A state signal indicates which synchronization clock is active. External interfaces derive timing from this distributed clock. Synchronized internal timing is provided by an internal clock and phase-locked loop (PLL) on each TM. The clock/PLL timing signal output is routed to other switch elements, enabling synchronized internal data transfer. Both interconnected TMs actively generate clock signals for external and internal use, enabling seamless timing switchover should conditions warrant a change in TMs.

Timing synchronization and switchover in a network switch

Growing community of inventors

Stoughton, MA, United States of America

Raymond Schmidt