Aurora Systems, Inc.

Rmi Corporation

Raymond Pinkham

W Spencer Worley, Iii

Edwin Lyle Hudson

John Gray Campbell

Hai Ngoc Nguyen

Yuanping Chen

An integrated circuit includes a phase-locked-loop with fast clock synchronization recovery. A phase frequency detector is configured to receive a system clock signal and a feedback clock signal and to generate a comparison signal. A clock generator is configured to general a first clock signal based on the comparison signal, and an internal clock signal. A controller coupled to the clock generator and configured to deliver a mesh clock signal to a global clock mesh. A synchronizer coupled to the control logic and configured to generate a feedback clock signal to the phase frequency detector. The mesh clock signal is provided from the global clock mesh to the synchronizer. Advantages of the invention include the ability to operate the integrated circuit in a sleep state with a slow clock rate and then quickly recover to an operational clock rate.

High performance integrated circuit with low skew clocking networks and improved low power operating mode having reduced recovery time

A flat panel display includes a plurality of pixel cells arranged in a rectangular matrix of columns and rows. Each pixel cell includes a pixel electrode, a primary storage element, and a switch for selectively coupling the pixel electrode with the primary storage element and a storage element of another pixel cell in an adjacent row or column. Columns and/or rows of redundant storage elements are provided, such that the switches of pixel cells in the last row or column of the display selectively couple the pixel electrode with a primary storage element and a redundant storage element.

Replacing defective circuit elements by column and row shifting in a flat-panel display

A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

System and method for reducing peak current and bandwidth requirements in a display driver circuit

A display driver circuit and method for receiving a display data stream, modifying the display data stream to enhance gray scale performance, and outputting the modified display data stream. The display driver includes a forced state generator for adding at least one forced state to the display data stream to create the modified display data stream. The forced state generator includes a multiplexer and a forced state controller. The multiplexer includes a data input terminal for receiving the display data stream, a first forced state input terminal for receiving first forced state data, a second forced state input terminal for receiving second forced state data, a data output terminal for outputting the modified display data stream, and a pair of control input terminals. The forced state controller includes a pair of control output terminals coupled the control input terminals of the multiplexer. Responsive to signals asserted on the control input terminals, the multiplexer selectively couples its data input terminal, its first forced state input terminal, and its second forced state input terminal with its data output terminal, thus generating the modified display data stream.

Growing community of inventors

Los Gatos, CA, United States of America

Raymond Pinkham