Texas Instruments Corporation

Other

Raymond Pinkham

Karl M Guttag

Donald J Redwine

Mark F Novak

Anthony M Balistreri

Andrew L Heilveil

Daniel F Anderson

Jerry R Vanaken

Jerry R VanAken

Fredrick A Valente

John Victor Moravec

Robert C Thaden

Jeffrey C Bond

A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register. The dual port memory containing the color register thus may rapidly store a bit-mapped graphical image where areas of the image are 'filled' with the same color information.

Read/write dual port memory having an on-chip input data register

Process of writing data from a data processor to a memory device

A read/write memory for use with a central processing unit is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. In response to a control signal generated in the read/write memory, the capacitor is connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored '1' value plus the dummy capacitor charge, for each of the bit lines to which it will be connected. Logic is incorporated into the memory to receive the data state to be written, and to receive the least significant bit of the row address. The logic connects the capacitor to the bit line to which the storage cell is connected in order to write a '0' state (the capacitor being precharged to ground), and connects the capacitor to the bit line to which the dummy cell is connected in order to write a '1' state. For a multiple input/output memory, a write mask may be included to inhibit the writing by the capacitor for selected arrays of the memory. A data input register may also be provided for storing the data to be written for multiple write cycles.

Read/write memory with plural memory cell write capability at a selected

A read/write memory is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. The capacitor may be connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored '1' value plus the dummy capacitor charge, for each of the bit lines to which it will be connected. Logic is incorporated into the memory to receive the data state to be written, and to receive the least significant bit of the row address. The logic connects the capacitor to the bit line to which the storage cell is connected in order to write a '0' state (the capacitor being precharged to ground), and connects the capacitor to the bit line to which the dummy cell is connected in order to write a '1' state. For a multiple input/output memory, a write mask may be included to inhibit the writing by the capacitor for selected arrays of the memory. A data input register may also be provided for storing the data to be written for multiple write cycles.

Read/write memory with selective row write capability

In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Video display system using memory with a register arranged to present an

In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Dual-port memory with inhibited random access during transfer cycles

Read/write memory having an on-chip input data register, having pointer

Video display system using memory with parallel and serial access

A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e., the first bit of the next group), the pass transistors are enabled so that the contents corresponding to the incremented contents of the stages above the break are next presented at the output. Logic is provided so that during serial input the stages are not broken, to prevent the early incrementing of the counter prior to storage of the input data. Logic is also provided so that, initially after the counter is loaded with a new value, the first bits are output without being disturbed by an early incrementing of the counter stages above the break.

Dual-port memory having pipelined serial output

A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs in inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simulaneously written with the contents of the color register. The dual port memory containing the color register thus may rapidly store a bit-mapped graphical image where areas of the image are 'filled' with the same color information.

Read/write memory having an on-chip input data register

In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e., the first bit of the next group), the pass transistors are enabled so that the contents corresponding to the incremented contents of the stages above the break are next presented at the output. Logic is provided so that during serial input the stages are not broken, to prevent the early incrementing of the counter prior to storage of the input data. Logic is also provided so that, initially after the counter is loaded with a new value, the first bits are output being disturbed by an early incrementing of the counter stages above the break.

A dual-port random access memory with multiple random inputs is disclosed which has a write mask register. The write mask allows a random write operation to occur on a subset of the random inputs, with the selected memory cells remaining undisturbed by the write operation. The write mask register provides for storage of the write mask information for a plurality of cycles, including intervening cycles which are unmasked writes. The write mask register may be loaded in two separate modes, either early in a cycle in conjunction with the row address strobe signal, or later in the cycle in conjunction with the write enable signal.

Multiple input/output read/write memory having a multiple-cycle write

A dual-port memory having a special operating mode (i.e., a block write mode) by which a plurality of memory cells may be written with the same data in a single write cycle is disclosed. The special mode is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. The column decoder in this device is in two stages, where the first stage selects a group of columns based upon the most significant column address bits. The second stage selects a single column based upon the least significant column address bits. In the block write mode, the result of the second column address decoder stage is ignored, and another set of signals select one, more than one, or all of the columns in the group for connection to the input/output circuitry, so that the same data is written to a plurality of memory locations within a certain column address proximity. The invention may be incorporated into a multiple input/output RAM, so that a plurality of columns, associated with a plurality of inputs, may be written in the same cycle. A color register is also provided to store the data to be written, so that the input terminals can be used to select which ones of the group of columns are to be written to in the block write mode. In the multiple input/output situation, a mask register may be provided to selectively inhibit the writing of certain ones of the inputs. The invention provides for efficient writing of color data to proximate memory locations, such a feature being especially useful in 'filling' an area in a bit-mapped image with a given color code.

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Missouri City, TX, United States of America

Raymond Pinkham