International Business Machines Corporation

Renesas Technology America, Inc.

Raymond Paul Rizzo

Daniel Mark Dreps

Hayden C Cranford, Jr

Carl Thomas Gray

Christopher G Riedle

John William Marshall

Robert Glen Gerowitz

Brian R Buchanan

Louis Regniere

A Network Interface Card (NIC) for attaching data terminal equipment to a communications network. The NIC includes a Phase Lock Loop (PLL) with a master delay structure that is operatively coupled to at least one delay line structure. The PLL generates control pulses at precise delayed intervals that are used to gate data through said at least one delay line structure.

Network interface card (NIC) with phase lock rise time control generating circuit

A method and apparatus are described for adaptively removing interference from a signal. A received signal is amplified linearly along a first signal path to provide a first signal and amplified nonlinearly along a second signal path to provide a second signal. The received signal propagates through the first and second signal paths at substantially the same time. The first and second amplified signals are mixed in proportion according to determined first and second weights, respectively, to provide an output signal having interference removed. The output signal is filtered to produce a first filtered signal corresponding to a ripple envelope of the output signal and filtered substantially simultaneously to produce a second filtered signal corresponding to an average peak detected value of the output signal. The first and second filtered signals are compared to produce an error signal. The first and second weights are determined according to the error signal.

Method and apparatus for adaptive equalization of high speed data communications

A system that generates data waveforms for transmission on a communications network includes a series of sequentially over sampled and switch current sources whose timings are locked to a master delay line and replicas thereof. The master delay is configured as a ring oscillator with its frequency looked to a precise clock reference. The clock controls the rise and fall of the data waveforms thus making them immune to variations in semiconductor processes used to implement the system.

DAC/Driver waveform generator with phase lock rise time control

A device and method that adjust data due to temperature variations is disclosed. The data is captured in a multi-stage delay line. A first controller parses the data and identifies an Edge value and an Edge value for bits in the delay line. The edge values are used to generate signals that set a Multiplexer (MUX ) and a Multiplexer (MUX ) to select bits from the delay line. A second controller processes an edge sample from bits in the delay line to determine if the data has shifted in the delay line relative to the current multiplexer settings. An edge sample is a snapshot of the delay line values. The new edge values generated by the second controller are selectively filtered and integrated with initial edge values to generate new settings for the MUX and MUX

System that compensates for variances due to process and temperature changes

A delay circuit arrangement includes a delay cell and controller. The delay cell includes a differential pair of N-Channel devices and P-Channel devices coupling the differential pair to positive voltage rail. The controller provides conductivity adjustment in the P-Channel devices. Adjustment of the delay is made by adjusting the current in a device biased in its linear region and coupling the differential devices to a ground potential.

Delay circuit arrangement for use in a DAC/driver waveform generator with phase lock rise time control

An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.

High speed parallel/serial link for data communication

An integrated D/A converter has a first feedback circuit for generating a first bias voltage to compensate for systemic changes. A second feedback circuit includes a plurality of switchable current sources biased by the first bias voltage and controlled by an externally supplied attenuation control signal to generate a second bias voltage which is applied to control the D/A current sources.

Controllable integrated linear attenuator for a D/A converter

An on-chip voltage controlled oscillator for use in an analog phase locked loop receives power from a voltage regulator which greatly reduces the noise seen by the voltage controlled oscillator. The voltage controlled oscillator has a DC bias section which supplies a relatively constant current to the multivibrator to assure a minimum operating frequency. A control signal is used to provide additional current which increases the speed of oscillation. The bias current reduces the transfer characteristics (MHz/volt) of the voltage controlled oscillator making it more immune to noise in the control signal.

On-chip voltage controlled oscillator

An oscillator comprises a comparator and first and second switches for alternately connecting first and second respective reference voltages to a first input of the comparator. A capacitor is connected to a second input of the comparator, and a current source and a current sink are alternately connected to the capacitor via third and fourth switches. The first and third switches are closed simultaneously based on one output level of the comparator, and the second and fourth switches are closed simultaneously based on the other output level of the comparator. This causes the output of the compartor to alternate and thereby generate an oscillation signal. To provide precision in the duty cycles, either the second reference voltage, the current source or the current sink is adjusted to maintain desired duty cycles of the high and low levels output from the comparator. The adjustment to the second reference voltage, current source or current sink is based on an average voltage of the capacitor in relation to a third reference voltage.

Oscillators having charge/discharge circuits with adjustment to maintain

A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer. The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.

Interface having serializer including oscillator operating at first

A differential transimpedance amplifier used in amplifying optical signals transmitted with a balanced code has a level restore circuit which integrates the digital output of the amplifier and feeds back the result to one of the differential inputs of the amplifier. The feedback signal removes imbalances from the amplifier output. The balanced amplifier output can then be processed by a clock reconstruction circuit to accurately sample the received optical signal with a low bit error rate.

Fiber optic amplifier with active elements feedback circuit

An amplifier circuit comprises first and second gain cells connected in cascade. Each of the gain cells comprises first and second common emitter differential transistors, a current source coupled to the emitters of the transistors, a first plurality of forward biased, series diodes connected between a power supply terminal and a base of the first transistor, and a second plurality of forward biased, series diodes connected between the power supply terminal and a base of the second transistor. A collector of the first transistor of the first gain cell is connected to the base of the first transistor of the second gain cell, and a collector of the second transistor of a first gain cell is connected to the base of the second transistor of the second gain cell. Because of the low inherent resistance of the biasing diodes, the operating speed of the amplifier is large, and the current amplification can be large without exceeding the power supply voltage. The current source limits the gain for high level signals without causing saturation of the transistors and therefore, does not comprise operating speed. The gain of each cell equals the numbers of diodes connected to the base of the transistor until the level of the current source.

Electronic gain cell

Monitor circuitry is placed in the closed loop of a phase-locked loop (PLL) circuit and is capable of detecting the existence of an out of frequency window condition and outputting a control signal when the PLL is operating outside the predetermined narrow frequency window. Recovery circuitry, including a phase frequency detector with a wide acquisition range, temporarily replaces the normal phase detector of the PLL, responsive to the control signal from the monitor circuitry. When the monitor circuitry determines that the PLL is back within the predetermined narrow frequency window, the PLL phase detector is switched back into the PLL loop and the phase frequency detector is removed from the PLL loop. The PLL phase detector is then able to lock in on the incoming data stream. In the preferred embodiment, the monitor and recovery circuitry and connected to a specialized PLL circuit which utilizes a 180 degree phase difference between incoming NRZ data and the recovered clock to strobe the data in the center of the input data pulse, thus improving the data error rate.

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Raleigh, NC, United States of America

Raymond Paul Rizzo