Motorola Corporation

Raymond P Voith

Sujit Sudhaman

James W Kimbrow

George P Hoekstra

Matthew A Pendleton

Charles D Robinson, Jr

A data interleaving system (20) provides flexibility by performing the interleaving function in a high level controller (32) and a separate low level controller (34). The high level controller (32) receives commands to operate on a codeword basis, in which a codeword is made up of a plurality of symbols which are grouped into a programmable number of frames. The low level controller (34) operates under the direction of the high level controller (32) on a symbol-by-symbol basis. By separating the codeword level tasks from the symbol level tasks, the data interleaving system (20) is able to accommodate various ratios of the number of frames per codeword without significant complexity. An analogous data de-interleaving system (220) includes a high level controller (232) and a low level controller (234).

Systems for programmably interleaving and de-interleaving data and

A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

Apparatus and method for clock recovery in a communication system

Interleaving/de-interleaving of data is achieved by storing and subsequently retrieving portions of the data from circular buffers (60,70). The circular buffers (60,70) are addressed such that each circular buffer corresponds to an index of data (B.sub.i). Thus, data (80) is written into a circular buffer (60,70) using a first modulo scheme and read using a second modulo scheme, where the second modulo scheme is based on the interleaving scheme. An index array (20) is used to point to the appropriate entry in the circular buffers(60,70) to ensure a proper interleave/de-interleave process.

Method and apparatus for interleave/de-interleave addressing in data

An interface (50) for a transceiver (5) for use in an asymmetric digital subscriber line (ADSL) system includes a routing table (200) which includes addresses of locations in a frame memory (150). When the transceiver (5) is operated as a central office transmitter input port data is received from several input ports. The routing table (200) addresses assign locations in the frame memory (150), corresponding to channels in the ADSL frame, which may be arbitrarily assigned. A control circuit (148) services the input ports by transferring data between the input ports and the address selected by the routing table (200). When operated as a remote terminal receiver, the transceiver (5) uses a routing table addressing the system except that the ports become output ports and frame memory (150) locations provide data to the output ports.

Interface for an asymmetric digital subscriber line transceiver

A transceiver (34) includes a rate adaptation buffer (74) that synchronizes a data stream received at a 4.0 kHz rate to a data stream that is transmitted at a 4.05 kHz rate. A transmit section (62) of the transceiver (34) performs rate adaptation using a single rate adaptation buffer. The transmit section (62) includes four autonomous modules which are able to access the data in the rate adaptation buffer (74) independently of one another. These four modules include a CRC-scrambler (72), a FEC encoder (76), an interleaver (78), and a constellation encoder (80). A timing controller (84) prevents contention for accesses to the rate adaptation buffer (74). In addition, each of the four modules perform their respective functions quickly enough to prevent overflow or underflow conditions in the rate adaptation buffer (74). A receive section (64) functions similarly to the transmit section (62).

Rate-adapted communication system and method for efficient buffer

In an ADSL transmitter (62), data is flamed and split between a fast path and an interleave path by multiplexer (66). Data is forward error correction encoded in FEC encoder (70). Data on the interleave path is interleaved by interleaver (72) if an interleave depth (D) is &gt;2. During interleaving, at least one additional read operation is performed, after a series of consecutive write and read operations. The additional read operation permits interleaving to continue without waiting for a next frame of data to arrive at the interleaver. An equal number of additional write operations compensates for the additional reads at a later point. Use of an interleaving memory can also be avoided by turning off or disabling the interleaver, while still permitting data to be sent along the interleave path. Transmit path controller (74) senses if D=1, and if so disables the interleaver and avoids the need for interleaver memory (64).

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Austin, TX, United States of America

Raymond P Voith