Ati Technologies Inc.

Ati Technologies Ulc

Ati International Srl

Raymond M Li

Milivoje M Aleksic

Carl K Mizuyabu

Danny H M Cheng

Anthony Asaro

Chun Wang

Antonio Asaro

Adrian H Hartog

Daniel Gudmundson

Antonio A Rinaldi

Indra Laksono

Allen J Porter

Oswin Hall

Henry Quan

An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.

Memory controller having plurality of channels that provides simultaneous access to data when accessing unified graphics memory

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

Memory device for providing data in a graphics system and method and apparatus thereof

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CHand CHaccess the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

Memory device for providing data in a graphics system and method and apparatus therof

A method and apparatus for combining video graphics processing and audio processing onto the same single chip and/or printed circuit board includes a graphics processing circuit, an audio processing circuit, a local bus, and a bus arbitrator. The local bus couples both the graphics processing circuit and audio processing circuit to the system bus such that each of the circuits may transceive data with the system bus. The bus arbitrator arbitrates access to the local bus between the graphics processing circuit and audio processing circuit. Such arbitration is based on incoming data, which is interpreted and, based on the interpretation, the bus arbitrator routes the incoming data to either the graphics processing circuit or the audio processing circuit. In addition, the bus arbitrator arbitrates outputting data from the graphics processing circuit and the audio processing circuit based on commands received from the CPU.

Method and apparatus of video graphics and audio processing

System of accessing data in a graphics system and method thereof

A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Display FIFO memory management system

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

Video controller for accessing data in a system and method thereof

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH and CH access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

A method and apparatus for customized editing and/or censoring of video and/or audio signals begins when a signal and a plurality of editing parameters are received. The signal includes an audio and/or video signal, where each of the editing parameters corresponds to separate portions of the signal. The editing parameters may be embedded within the signal or provided in simulcast with the signal. While the signal is being processed, a selective editing circuit is monitoring the editing parameters. When an editing parameter indicates that the corresponding portion of the signal is to be edited, the selective editing circuit edits the corresponding portion based on the editing parameter, which may be provided by the content provider or the user. In addition, the editing parameter may indicate various levels of editing the signal. For example, the editing parameter may indicate that the portion of the audio and/or video signal is to be completely blanked, skipped, faded, distorted, or is to be replaced with a substitute audio and/or video signal.

Method and apparatus for customized editing of video and/or audio signals

A method and apparatus for processing data of different sizes begins by processing first data to produce an n-bit resultant. Such processing may be performing an arithmetic function upon the data. In addition, second data is processed to produce an m-bit resultant. Such processing of the second data may also include performing an arithmetic function upon the second data. The processing then continues by mixing the n-bit resultant with the m-bit resultant to produce an m-bit mixed resultant. For example, the first data may be representative of RGB graphics data that is processed by a graphics core to produce an 8-bit resultant. The second data may be representative of video data that is processed by a video core to produce a 10-bit resultant. A mixer mixes the 8-bit graphics output with the 10-bit digital video output to produce a 10-bit mixed output. A digital-to-analog converter converts the 10-bit mixed output into an analog signal.

Method and apparatus for processing data as different sizes

A video display apparatus and method for displaying decoded video frames from an encoded video stream utilizes a display time difference determinator that detects a frame display time difference, on a per frame basis if desired, between a refresh rate based frame display time, and a video playback frame rate display time to generate frame display time difference data. This is done on a continuous basis to detect synchronization problems between video data that is to be displayed simultaneously with non-video data on a display device such as a progressive display screen. A pixel blender blends pixel data from an adjacent frame, such as an already reconstructed previous frame or next frame, to create a temporally adjusted frame based on the determined frame display time difference data.

Video display method and apparatus with synchronized video playback and weighted frame creation

A multiple pipeline memory controller has a plurality of two stage pipeline processors dedicated to separately process real time video capture and display refresh input request signals. A separate pipeline processor processes non-real time input signals. The multiple pipeline design reduces memory access latency and improves throughput of data in display FIFO memory to effect improved resolution. The multiple pipeline memory controller can be integrated in a video graphics controller (VGC).

Multiple pipeline memory controller for servicing real time data

A method and system to automatically align overlaying video data on a computer screen based on input information of R or G or B data, horizontal synchronization signal data (Hsync) and vertical synchronization signal data (Vsync) automatically reconstructs a pixel clock time base of an offboard underlying graphics source for use in aligning overlaid video using a generated vertical pixel pattern. The system and method also automatically detects a size of an active computer screen region and position of a top left hand corner and a bottom right hand corner of the active computer screen region to align overlaying video using the reconstructed pixel clock time base and a single color block pattern.

Automatic video overlay alignment method and apparatus

A gamma correction circuit comprising circuit apparatus for approximating in linear translation circuits successive nonlinear portions of a gamma correction curve, apparatus for applying an input luminance (Y) signal to the circuit apparatus, and selection apparatus for selecting signals translated by any of the circuit apparatus as a gamma corrected output signal depending on whether the input signal falls within predetermined ranges approximately corresponding to the nonlinear portions of the gamma correction curve.

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Markham, Canada

Raymond M Li