Cypress Semiconductor Corporation

Raymond M Leong

Mathew R Arcoleo

Derek R Johnson

Charles D Stormon

Nikos B Troullinos

Jonathan F Churchill

Peter H Voss

Thurman John Rodgers

Piyush Sevalia

Abhijeet Chavan

Edward Saleh

Tek Wei

A circuit comprising a memory array and a control circuit. The memory array generally comprises a plurality of storage queues. Each of the storage queues may be configured to (i) receive and store an input data stream and (ii) present an output data stream. The storage queues may be configured to operate either (i) independently or (ii) in combination to store the input data streams, in response to one or more control signals. The control circuit may be configured to present the one or more control signals to control an operation of the plurality of storage queues. The control signals may be configured to control the configuration of the plurality of storage queues.

Multiport FIFO with programmable width and depth

An integrated circuit and computer system. According to one embodiment of the present invention an integrated circuit on a single substrate for use with a microprocessor which is coupled to a processor bus is provided, and the integrated circuit includes a cache random access memory array and a data path logic control unit, such as multiplexer which is coupled to the cache random access memory array and has an output for coupling to the processor bus. In one embodiment, a further multiplexer having an output for coupling to a first portion of a memory is provided, and this multiplexer further has input for coupling to a second portion of the memory bus. The IC according the present invention is also for use with a second IC which includes control logic for controlling system memory and for controlling the processor bus and memory bus as well as interfacing to other buses such as peripheral bus. The present invention also provides for improved layout of a cache array with a data path logic management unit as well as power management features for the cache array and a tag RAM with comparator on, in one embodiment, the same chip with the cache array or on an associated chip in another embodiment.

Integrated cache memory with system control logic and adaptation of RAM

A memory array comprising a plurality of storage elements and a logic circuit. The memory array may be configured to (i) receive a plurality of input data streams, (ii) store each of the plurality of input data streams in one or more of the storage elements in response to a plurality of control signals and (iii) present a plurality of output data streams in response to the plurality of input data streams. The logic circuit may present the plurality of control signals in response to the fullness of each of the plurality of storage elements.

Cascadable multi-channel network memory with dynamic allocation

An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device. Since the output buffer circuit of the invention allows the output buffer drive strength to be more closely tailored to the electrical load being driven, signal reflections, voltage overshoot and undershoot, and timing problems that can result from mismatch between the output buffer drive strength and the associated electrical load can be reduced.

Memory having selectable output strength

An associative processing memory system for concurrent data searching and concurrent data processing which includes content addressable memory (CAM) array having multiple CAM words; a multiplexer for executing one of the input devices and for passing an output of one of the input devices; an interface register logic block for storing instructions in a command register and control and status information in a control and status register; a match circuit for executing a match instruction for performing a masked comparison of data in every CAM word in the CAM array to a search pattern; a read circuit for executing a read instruction for reading one CAM word in the CAM array wherein the CAM word is selected using a response register A and a multiple response resolver (MRR); a write circuit for executing a write instruction for performing a masked write operation to every CAM word indicated by a bit set in a select vector; a shift circuit for executing a shift instruction for shifting the response register A up or down by one bit position; a clear circuit for executing an instruction for clearing the most significant bit set in the response register A; a move circuit for executing a move instruction for writing the data contents indicated by the select vector to a response register; a write-column circuit for executing an instruction for writing the contents of the select vector to a column in the CAM array; a circuit for executing an nop instruction for performing no operation; a read-shift for executing a readshift instruction; a read-snext circuit for executing a readsnext instruction; a write-shift circuit for executing a writeshift instruction; and a write-snext circuit for executing a writesnext instruction.

Instruction set for a content addressable memory array with read/write

A Static Random Access Memory (SRAM) comprises an input/output pin and driver means connected to the input/output pin. The driver means are configured to drive the input/output pin to a voltage potential using a first current, and are further configured to hold the input/output pin at approximately the voltage potential using a second current. In one embodiment, the driver means may comprise a driver unit for driving the input/output pin to the voltage potential, a bus hold circuit for holding the input/output pin at the voltage potential and a control unit connected to the driver unit and the bus hold circuit. The control unit may activate and deactivate the driver unit and the bus hold circuit.

Method and circuit for preventing and/or inhibiting contention in a

An associative processing memory system for concurrent data searching or processing includes a content addressable memory (CAM) array, a general register block, an interface register logic block, and a general control block. The CAM array is accessed for read or write by a select vector generated by the general register logic block. The select vector is selected through a multiplexer from at least four sources: the match latch, the multiple response resolver, the general purpose logic block and a supplies one unit. The interface register logic block provides input/output data registers, mask register, command register, and control/status register. The general control block generates control signals to the CAM system in response to bus signals. The match operation for the CAM array can be performed on all words in a single operation. A set of CAM instructions is used to control CAM operations including data movement, shifting, read/write, and match.

Integrated content addressable memory array with processing logical and

A resettable SRAM architecture and method that eliminates the need to reset all memory cells in the data memory array and requires only the resetting of one flag bit per block of data. This prevents superfluous activation of access circuits and memory cell transistors, thereby reducing power consumption and parasitic noise.

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Los Altos, CA, United States of America

Raymond M Leong