Integrated Device Technology, Inc.

Intel Corporation

Raymond M Chu

David J Pilling

Sik K Lui

De H Nguyen

Vishal Sarin

John R Mick

Walter E Croft

Alex E Henderson

A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.

Match resolution circuit for an associative memory

A circuit and method for reading and writing to a microprocessor's internal cache memory during a test mode of operation. During write accesses, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with an external clock. During read accesses, the external data bus transmits an address and receives from the internal data bus data and cache tags. In one embodiment, during a write access, the external data bus is time-multiplexed to transmit an address, cache tags and data in two clock periods of the external clock the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal and to receive tag and data in the next successive clock periods of the external clock signal. In this embodiment, reserved pins are used to specify a cache access mode, including a test mode of operation. During the test mode, read and write buffers for the internal cache are deselected from the interal bus and the central processing unit of the microprocessor is stalled. Control for the cache access is provided via pins which are used during functional (non-test mode) operation to receive external interrupt signals.

Test mode accessing of an internal cache memory

An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup transistor and a pulldown transistor. The two pullup and pull down transistors are coupled in series between two drive transistor circuits. In one aspect of the invention, the pullup and pulldown drive transistor circuits provide momentary low impedance connection of the pullup and pulldown transistors to the respective pullup and pulldown voltage sources during the initial switching waveforms of the digital signal. After the initial switching of the digital signal, the pullup and pulldown drive transistor circuits provide precise V.sub.OH and V.sub.OL voltage output levels and provide high impedance filtering of voltage supply line and ground line noise. In another aspect of the invention, the high frequency response of the output is enhanced by auxiliary pullup and pulldown drivers in parallel with the pullup and pulldown output transistors. These auxiliary pullup and pulldown drivers reduce the switching time of the digital signal output to provide increased frequency response even in a high capacitance loaded environment.

Output driver circuit for high speed digital signal transmission

A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage address registers, with an address register being provided for each address bit. Prior to an initial rising edge of the clock signal, an initial address is loaded into the first stages of the two-stage address registers. In response to the initial rising edge of the clock signal, the initial address is clocked through the second stages of the two-stage address registers, directly to the memory. Subsequent addresses are derived from the initial address by circuitry within the burst address sequencer. These subsequent burst addresses are provided to the first stages of the addresses registers prior to subsequent rising edges of the clock signal and clocked out to the memory in response to these subsequent rising edges of the clock signal. By providing the addresses directly from the second stage of the address registers to the memory, the logic gate delay associated with providing the addresses to the memory in response to the rising edge of the clock signal is minimized.

Interleaved burst address counter with reduced delay between rising

A circuit improves the reliability of antifuses in certain types of systems by substantially eliminating the continuous undesirable applications of voltages across antifuse terminals. To accomplish this, an antifuse has applied across its two terminals a 'reading' or 'evaluation' voltage as required by the system operation for a single read or evaluation clock period (typically 5 ns to 30 ns in duration). The signal describing the state of the antifuse is then stored in a latch, register, or other suitable structure for subsequent sampling. In this manner, a low read current flows in the antifuse in response to the standard chip operating voltage for only a short period of time such as a single clock cycle. Thus, continuous voltages across the two terminals of the antifuse are avoided and an unprogrammed antifuse is not inadvertently programmed and a programmed antifuse is not inadvertently converted back to its high impedance state (i.e. 'unprogrammed'). In another embodiment, a multiplexer coupled to a terminal of the antifuse switches the terminal of the antifuse to a programming voltage node when the antifuse is selected for programming and to a reference voltage source when the antifuse is not selected for programming. The multiplexer prevents undesired voltages from being applied across the antifuse while other antifuses are being programmed. The two embodiments discussed may be used in conjunction with each other or separately.

Circuits for improving the reliability of antifuses in integrated

An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.

Redundancy circuit for programmable integrated circuits

Integrated circuit access times are reduced by an input structure in which input signals are routed through a low resistance path from the input pad directly to the interior of the integrated circuit without using an input driver.

Input structure for digital integrated circuits

Circuits for improving the reliablity of antifuses in integrated circuits

A method and structure for logically disconnecting an on-chip virtual-to-physical address translation unit from a microprocessor by holding the dynamic circuits of the translation unit in precharged state. In one embodiment, the method and structure provide a fixed remapping for the virtual address. A powering down of the translation unit effects power savings when the translation unit is not required.

Logically disconnectable virtual-to-physical address translation unit

A high resolution sense amplifier and method for sensing the state of antifuses in an integrated circuit is capable of correctly reading even a defectively programmed antifuse having a resistance of up to 20 K.OMEGA. as being programmed. The sense amplifier reads two antifuses at each programmable location, and correctly reads that location as being programmed if either or both of the antifuses at that location have been blown.

Growing community of inventors

Saratoga, CA, United States of America

Raymond M Chu