Motorola Corporation

Other

Raymond Louis Barrett

Barry W Herold

Grazyna A Pajunen

Scott R Humphreys

Walter L Davis

James G Mittel

Edgar Herbert Callaway, Jr

John Wayne Simmons

Douglas H Weisman

Gilberto Jacinto Hernandez

Grazyna Anna Pajunen

Lawrence L Case

Lawrence Loren Case

The method and apparatus described herein uses modern digital logic that is used to meet the need by controlling Switch-Mode Power System (SMPS) components to produce efficient conversion of the AC input source to a DC output load, maintain a near-unity Power Factor Control (PFC), require relatively small components for energy storage and filtering, as well as support a form of soft-start load application to a Poly-Phase AC source.

Method and apparatus for digital power factor correction of a poly-phase AC to DC converter

A transmission line ( ) is formed to have a characteristic impedance which increases at a first substantially exponential rate with respect to a distance from the input ( ). A plurality of resonators ( ) are coupled to the transmission line and positioned at a plurality of locations along the transmission line. The plurality of resonators has resonant frequencies that decrease at a second substantially exponential rate with respect to the distance from the input. An output signal ( ) is obtained at a point in the filter that produces a filter response having a corner frequency.

Method and apparatus for creating a radio frequency filter

A circuit ( ) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector ( ) and a sigma-delta analog-to-digital converter ( ). The FM ratio detector ( ) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter ( ), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic &ldquo;1's&rdquo; and logic &ldquo;0's&rdquo; that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal ( ).

Sigma delta FM ratio detector

A selective call receiver (,) includes a radio receiver (,) and a processor (,). The radio receiver includes an antenna (,), a combination circuit (,), a bandpass filter (,), mixers (,), analog-to-digital converters (,), digital mixers (,), a second combination circuit (,), and a digital-to-analog converter (,). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.

Selective call receiver having an apparatus for modifying an analog signal to a digital signal and method therefor

A random number generator includes a sample clock having a sample clock rate, a chaotic oscillator having a characteristic upper frequency, and an output section. The chaotic oscillator includes a quantized linear section and a non-linear section. The quantized linear section includes multiple quantized integrators coupled to the sample clock and intercoupled in a linear intercoupling. The non-linear section is coupled in a feedback manner with the quantized linear section. The output section generates a random binary output signal having the sample clock rate, formed by a logical combination of binary signals, of which one binary signal is generated by each of the multiple quantized integrators. Each quantized integrator includes an analog to digital converter that preferably includes a sigma delta converter that generates one of the binary signals.

Binary random number generator

A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.

Low power precision current reference

A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.

Low power precision voltage splitter

A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).

Band-pass sigma-delta converter and commutating filter therefor

A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.

Method and apparatus for frequency synthesis

A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.

Two's complement digital to analog converter

A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).

Method and apparatus for extending an operating frequency range of an

A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.

Fast starting oscillator

A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.

Method and apparatus for controlling a phase lock loop

A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N.sup.2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node. The N control lines control the controllable switches in a predetermined sequence.

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Ft. Lauderdale, FL, United States of America

Raymond Louis Barrett