Microsoft Technology Licensing, LLC

Raymond Leonard Kallaher

Geoffrey Charles Gardner

Michael James Manfra

Sergei Vyatcheslavovich Gronin

Sergei Vyacheslavovich Gronin

Flavio Griggio

Noah Seth Clay

Roman Mykolayovych Lutchyn

Peter Krogstrup Jeppesen

Georg Wolfgang Winkler

Andrey Antipov

Dmitry Igorevich Pikulin

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same

A laser emitter is provided, including a substrate and a dielectric mask layer located proximate to and above the substrate in a thickness direction. The dielectric mask layer may have a plurality of trenches formed therein. The plurality of trenches may have a plurality of different respective widths. The laser emitter may further include a respective nanowire located within each trench of the plurality of trenches. Each nanowire may include a first semiconductor layer located above the substrate in the thickness direction. Each nanowire may further include a quantum well layer located proximate to and above the first semiconductor layer in the thickness direction. Each nanowire may further include a second semiconductor layer located proximate to and above the quantum well layer in the thickness direction.

Laser emitter including nanowires

The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 Å. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.

Sag nanowire growth with a planarization process

The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.

SAG nanowire growth with ion implantation

Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount. The method further includes forming a superconducting layer over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.

Forming semiconductor-superconductor hybrid devices with a horizontally-confined channel

SAG nanowire growth with a planarization process

A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.

Graded planar buffer for nanowires

A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.

Fabrication of a device

A method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.

Method for manufacturing nanowires

A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.

Selective area growth with improved selectivity for nanowires

A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.

Nanowire with reduced defects

A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

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West Lafayette, IN, United States of America

Raymond Leonard Kallaher