Tektronix, Inc.

Tektronix International Sales Gmbh

Raymond L Veith

Yasumasa Fujisawa

Steven K Sullivan

Iwao Akiyama

Laszlo J Dobos

Jeffrey D Earls

Gordon Alan Olsen

Yukio Aizawa

Kelly F Garrison

An automatic quadrature network with amplitude and phase detection produces quadrature signals for an input oscillator signal, the quadrature signals being equal in amplitude and having ideal quadrature phase between them. An RC circuit provides one quadrature path, and a CR circuit provides another quadrature path. The outputs from the RC/CR circuits are amplitude detected to produce an amplitude control signal. The outputs also are amplitude limited, and the phase between the limiter outputs is detected to produce a phase control signal. The amplitude and phase control signals are combined to generate respective control signals for the RC/CR circuits to automatically align them so that the quadrature signals are of equal amplitude and ideal quadrature phase.

Automatic quadrature network with phase and amplitude detection

A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channelsandhave signal generation blocksandthat have clock phase shift circuitsand, memories, parallel to serial converters and DACs respectively. A phase comparatorcompares data reading clocks from the signal generation blocksandto produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocksand. A CPU controls the clock phase shift circuitsandaccording to the phase difference signal to shift phases of the clocks provided to the signal generation blocksandand then makes phase relationship between the output signals of the first and second channelsandas desired.

Phase controllable multichannel signal generator having interleaved digital to analog converters

A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channelsandhave signal generation blocksandthat have clock phase shift circuitsandmemories, parallel to serial converters and DACs respectively. A phase comparatorcompares data reading clocks from the signal generation blocksandto produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocksandA CPU controls the clock phase shift circuitsandaccording to the phase difference signal to shift phases of the clocks provided to the signal generation blocksandand then makes phase relationship between the output signals of the first and second channelsandas desired.

Phase controllable multichannel signal generator

A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.

DDS pulse generator architecture

A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

Triggered DDS pulse generator architecture

A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples. An optional infinite track-and-hold circuit may be used to generate corrected replica phase values that replace the corrected phase values for longer sample delay periods.

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Portland, OR, United States of America

Raymond L Veith