Fujitsu Corporation

Fujitsu Network Communications, Inc.

Other

Digital Equipment Corporation

Raymond L Strouble

Stephen A Caldara

Thomas A Manning

Stephen A Hauser

Rebecca L Stamm

Douglas H Hunt

John H Edmondson

Nicholas D Wade

Michael Sluyski

Richard Lee Sites

Derrick R Meyer

Ernest P Walker

Douglas E Sanders

Michael E Gaddis

Michael A Callander

Richard G Bubenik

James M Meredith

Linda Chao

Ruth I Bahar

R Iris Bahar

David Archer

Samyojita Nadkarni

Mary C Stock

An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Data encoder/decoder for a high speed serial link

A method and apparatus for providing buffer state accounting at a link level, otherwise known as link flow control, in addition to flow control at the virtual connection level. Link flow control enables receiver cell buffer sharing while maintaining per-connection bandwidth with lossless cell transmission. High link level update frequency is enabled without a significant sacrifice in overall link forward bandwidth. A higher and thus more efficient utilization of receiver cell buffers is achieved.

Method and apparatus for providing buffer state flow control at the link level in addition to flow control on a per-connection basis

A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switch is used to change from the parallel test mode to the scan test mode. A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode. The speed of the scan test mode is increased by interleaving the memory and reading test vectors out of the memory in parallel. Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT). Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.

Test system for integrated circuits using a single memory for both the

Methods and apparatus for scheduling cell transmission over a network link by a switch. The switch includes a plurality of queues associated with each link. Lists of queues are maintained for each link. In one embodiment, each link is associated with more than one type of list (with the list type corresponding to a scheduling category) and more than one prioritized list of each type (with the priority of the list corresponding to a quality of service). The scheduling lists are accessed to permit cell transmission from a queue contained therein in a predetermined sequence as a function of scheduling category, priority within a particular scheduling category and whether the bandwidth requirement for the particular scheduling category has been met. With this arrangement, maximum permissible delay requirements for each scheduling category are met.

Network link access scheduling using a plurality of prioritized lists

A method and apparatus is disclosed for allocating bandwidth within a network switch having a plurality of input ports coupled to a plurality of output ports through a switch fabric to assure that a minimum bandwidth is allocated for predetermined scheduling lists. A switch allocation table is provided for each of a plurality of input ports. Each switch allocation table is organized as a circular table which is sequentially indexed via an associated index counter. Respective entries in the switch allocation table comprise scheduling list numbers which serve to identify cells requiring switch bandwidth. The respective index counters are synchronized such that all switch allocation tables have a corresponding entry selected. The amount of bandwidth and delay through the network switch is controlled for each of the scheduling lists based upon the number and spacing of entries in the respective switch allocation table. Latency through the network switch is significantly reduced via the use of a pace counter and a pace limit which, in cooperation with the switch allocation table, determine whether a cell associated with a particular scheduling list may be dispatched through the switch fabric for transmittal onto a network link by at least one of the output ports.

Controlling bandwidth allocation using a pace counter

A method and apparatus for providing buffer state accounting at a link level, otherwise known as link flow control, in addition to flow control at the virtual connection level. Link flow control enables receiver cell buffer sharing while maintaining perconnection bandwidth with lossless cell transmission. High link level update frequency is enabled without a significant sacrifice in overall link forward bandwidth. A higher and thus more efficient utilization of receiver cell buffers is achieved.

Method and apparatus for providing buffer state flow control at the link

A linked-list structure and method for use in an ATM network switch capable of adaptively providing highly efficient, and thus low cost, integrated services therein. The linked-list structure involves the creation of a list having pointers to a subsequent linked list as list entries. Within the subsequent linked list, each entry can be a pointer to a further linked list. The structure can be expanded to further levels of linked lists as required. Bandwidth distribution is thus achieved among list members at each level. The linked-list structure is employed in the present switch, which includes an input port processor, a bandwidth arbiter, and an output port processor, for switch bandwidth scheduling for both point-to-point, multipoint-to-point and point-to-multipoint cell transfers from the input port processor, and for output link scheduling at the output port processor.

Linked list structures for multiple levels of control in an ATM switch

Link buffer sharing method and apparatus

Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that provides limited use of the data in the cache; a read or write request for data not owned in the cache is made to the main memory instead of the cache, even when the data is valid in the cache, although owned data is read from the cache. In ETM, when the processor makes a first write request to data not owned in the cache followed by a second write request to data owned in the cache, write data of the first write request is prevented from being received by the main memory after write data of the second request while permitting writeback of the data owned by the cache. Preferably this is done by sending the write requests from the processor through the non-writeback queue, and when a write request accesses data in a block of data owned by the cache, disowning the block of data in the cache and writing the disowned block of data back to the main memory.

Ensuring write ordering under writeback cache error conditions

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

Processor system with writeback cache using writeback and non writeback

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency. For CAL type instructions, a method for determining which registers need to be saved is executed in a minimum number of cycles, examining groups of register mask bits at one time. Internal processor registers are accessed with short (byte width) addresses instead of full physical addresses as used for memory and I/O references, but off-chip processor registers are memory-mapped and accessed by the same busses using the same controls as the memory and I/O. In a non-recoverable error detected by ECC circuits in the cache, an error transition mode is entered wherein the cache operates under limited access rules, allowing a maximum of access by the system for data blocks owned by the cache, but yet minimizing changes to the cache data so that diagnostics may be run. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

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Westford, MA, United States of America

Raymond L Strouble