Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Globalfoundries Singapore Pte. Ltd.

Raymond Joy

Liang Choo Hsia

Boon Meng Seah

Timothy Joseph Dalton

Mei Sheng Zhou

Simon Yew-Meng Chooi

John Leonard Sudijono

Henry K Utomo

Sanford Chu

Nicholas C M Fuller

Pietro Montanini

Bei Chao Zhang

Chit Hwei Ng

Lup San Leong

Chaw Sing Ho

Ramasamy Chockalingam

Paul Kwok Keung Ho

Wuping Liu

Chun Hui Low

Beichao Zhang

Shao Kai

Wen Jun Liu

Sajan Marokkey Raphael

Shyam Pal

Yi-hsiung Lin

Marta Mottura

Ba Tuan Pham

Thomas Schulue

Premachandran Vayalakkara

Shao Beng Law

Wai Lok Lee

A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Prevention of faceting in epitaxial source drain transistors

An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.

Apparatus and methods for cleaning and drying of wafers

An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects

Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

Multiple layer resist scheme implementing etch recipe particular to each layer

An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing. In addition, the method of forming the MIM capacitors, described herein, can also be used to form anti-fuse devices, in field-programmable gate arrays, FPGA.

MIM and metal resistor formation at CU beol using only one extra mask

A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer and a metal layer is deposited overlying the barrier metal layer. The metal layer is covered with a photoresist mask wherein there are both wide spaces and narrow spaces between portions of the photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask wherein the barrier metal layer is reached within the wide spaces while some of the metal layer remains within the narrow spaces. The metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the barrier metal layer not covered by the photoresist mask is etched away wherein the insulating layer is reached within the wide spaces while some of the barrier metal layer remains within the narrow spaces. The barrier metal layer remaining within the narrow spaces is selectively etched away. Thereafter, the insulating layer not covered by the photoresist mask is overetched to complete the metal lines without microloading in the fabrication of an integrated circuit.

Method to reduce microloading in metal etching

An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been developed. The method is a five step process, in which the first step is in a microwave generated plasma containing O,and H,O; the second step is in a microwave generated plasma containing O,and N,; the third step is in a microwave generated plasma containing H,O; the fourth step is in a microwave generated plasma containing O,and N,; and the fifth step is in a microwave generated plasma containing H,O. The first step which initiates removal of photoresist while simultaneously beginning the passivation process causes residue-free removal of photoresist following etching of aluminum or aluminum-copper layers in chlorine bearing etchants.

Post metal etch photoresist strip method

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Singapore, Singapore

Raymond Joy