Tokyo Electron Limited

Raymond Joe

Anthony Dip

Sanjeev Kaushal

Meenakshisundaram Gandhi

Pradip Kumar Roy

Takanori Saito

Pradeep Pandey

Kenji Sugishima

Seungho Oh

John Gumpher

Allen John Leith

David Smith

Sundar Gandhi

A method is provided for depositing silicon and silicon-containing films by atomic layer deposition (ALD). The method includes disposing the substrate in a batch processing system configured for performing ALD of the silicon-containing film, exposing the substrate to a non-saturating amount of a first precursor containing silicon, and evacuating or purging the first precursor from the batch processing system. The method further includes exposing the substrate to a saturating amount of a second precursor containing silicon or a dopant, where only one of the first and second precursors contain a halogen, and a reaction of the first and second precursors on the substrate forms a silicon or silicon-containing film and a volatile hydrogen-halogen (HX) by-product, evacuating or purging the second precursor and the HX by-product from the batch processing system, and repeating the exposing and evacuation or purging steps until the silicon or silicon-containing film has a desired thickness.

Atomic layer deposition of silicon and silicon-containing films

A method is provided for low temperature catalyst-assisted atomic layer deposition of silicon-containing films such as SiOand SiN. The method includes exposing a substrate surface containing X&#x2014;H functional groups to a first R&#x2014;X&#x2014;Rcatalyst and a gas containing silicon and chlorine to form an X/silicon/chlorine complex on the surface, and forming a silicon-X layer terminated with the X&#x2014;H functional groups by exposing the X/silicon/chlorine complex on the substrate surface to a second R&#x2014;X&#x2014;Rcatalyst and a X&#x2014;H functional group precursor. The method further includes one or more integrated in-situ reactive treatments that reduce or eliminate the need for undesired high-temperature post-deposition processing. One reactive treatment includes hydrogenating unreacted X&#x2014;H functional groups and removing carbon and chlorine impurities from the substrate surface. Another reactive treatment saturates the silicon-X layer with additional X&#x2014;H functional groups.

Catalyst-assisted atomic layer deposition of silicon-containing films with integrated in-situ reactive treatment

A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

Silicon germanium surface layer for high-k dielectric integration

A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.

Method for extending time between chamber cleaning processes

Photoresist stripping is provided that employs batch processing to maximize throughput and an upstream plasma activation source using vapor or gas processing to efficiently create reactive species and minimize chemical consumption. An upstream plasma activation source efficiently creates reactive species remote from the photoresist on the substrate surfaces. Either a remote plasma generator upstream of the processing chamber or an integrated plasma unit within the processing chamber upstream of the processing volume may be used. Plasma processing gas is introduced from a side of a stack of wafers and flows across the wafers. Processing gas may be forced across the surfaces of the wafers in the column to an exhaust on the opposite side of the column, and the column may be rotated. An upstream plasma activation source enables a strip process to occur at low temperatures, for example below 600 degrees C., which are particularly advantageous in BEOL process flow. Integrated processes that combine dry and wet-like sequential processes are also provided. Oxidizing, reducing or fluorine-containing plasma can be employed. Wet stripping, using, for example, wafer vapor or ozone or both may be included, simultaneously or sequentially.

Batch photoresist dry strip and ash system and process

A method for forming an oxide layer on a substrate. The method includes exposing a process gas containing H, an oxygen-containing gas, and a halogen-containing oxidation accelerant gas to the substrate, where the process chamber is maintained at a subatmospheric pressure, and forming an oxide layer through thermal oxidization of the substrate by the process gas. According to one embodiment of the invention, the substrate can be maintained at a temperature between about 150&#xb0; C. and about 900&#xb0; C. A microstructure containing an oxide layer is described, where the oxide layer can be a gate dielectric oxide layer or an interface oxide layer integrated with a high-k layer.

Method of forming an oxide layer

A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response for the processing chamber during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BIST table.

Built-in self test for a thermal processing system

A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.

Low-temperature plasma-enhanced chemical vapor deposition of silicon-nitrogen-containing films

A semiconductor wafer susceptor for batch substrate processing. The susceptor includes a central region in a primary plane and a plurality of flat annular extensions extending below the central region in a secondary plane. The primary and secondary planes are parallel to each other. An edge of the substrate overhangs the central region allowing no contact of the susceptor with the substrate edge.

Semiconductor wafer susceptor

A removable semiconductor wafer susceptor used for supporting a substrate during batch processing. The susceptor includes a flat circular central plane with a predetermined outer diameter. The susceptor is sized to fit within an inner diameter formed from wafer support ledges of a wafer transport container. The susceptor includes edges that are chamfered and rounded to lessen stress concentration at the edges. The susceptor is transported through processing by a sieving action of transport automation.

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Austin, TX, United States of America

Raymond Joe