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Mosaid Technologies Corporation

Raymond Jit-Hung Sung

Tyler Lee Brandon

John Conrad Koob

Duncan George Elliott

Duncan George Elliot

Daniel Arie Leder

A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines

The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.

Method for scalable architectures in stackable three-dimensional integrated circuits and electronics

A circuit and method for accelerating bus line communication in an integrated circuit is disclosed. High speed transmission of signals along a bus line is achieved by driving a series of bus line segments with their own bi-directional bus amplification circuits. Because each bus line segment has less capacitive loading than longer non-segmented bus lines, voltage reversal, or data inversion of a pair of complementary lines of a bus line segment is accomplished at high speed. Each bi-directional bus amplification circuit includes a precharge circuit for precharging each complementary pair of lines to known logic levels, and a drive circuit for changing the logic level of each line. The bi-directional bus amplification circuit of the present invention logically connects two lines to each other while actively amplifying the signal in either direction without prior knowledge of which direction the signal must be driven, and without additional control overhead than that required for a conventional precharged bus line.

Bi-directional amplifier and method for accelerated bus line communication

A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.

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Wilmington, MA, United States of America

Raymond Jit-Hung Sung